Abstract: Provided is an optical transmitter including, a substrate (silicon optical bench), a light emitting element, and a temperature sensing element; wherein, two recesses are formed in a surficial portion of the silicon optical bench; the light emitting element is provided inside one recess; and the temperature sensing element is provided inside the other recess.

Abstract: In a semiconductor device, a first semiconductor chip includes a first circuit and a first inductor, and a second semiconductor chip includes a second circuit and chip-side connecting terminals. An interconnect substrate is placed over the first semiconductor chip and the second semiconductor chip. The interconnect substrate includes a second inductor and substrate-side connecting terminals. The second inductor is located above the first inductor. The chip-side connecting terminals and the two substrate-side connecting terminals are connected through first solder balls.

Abstract: It is desired for semiconductor devices to reduce an inrush current and an overshoot. According to the voltage regulator circuit of the present invention, when a power supply is turned on, a switch SW1 is turned on in response to a control signal CTR1, a switch SW2 is turned off, and a reference voltage Vref is input to the first (+IN) and second (?IN) inputs of a differential amplifier AMP1 as a common voltage. When a common voltage is supplied to the first (+IN) and second (?IN) inputs, the current I flows into a smoothing capacitor C1 from the high-voltage power supply (VDD) via the differential amplifier AMP1 is regulated to be small. Namely, an inrush current can be reduced. Further, according to the voltage regulator circuit 30 of the present invention, the increase of the output voltage Vout from the differential amplifier AMP1 is relaxed so that the overshoot can be suppressed.

Abstract: Control accuracy with regard to variation of output voltage is improved. A direct current converter unit (20) that steps up or steps down an input voltage (Vin) to be outputted, and a control unit (10) that controls output voltage (Vout) of the direct current converter unit (20) by a pulse width modulation signal (Sw) are provided; the direct current converter unit (20) is provided with a voltage detection circuit (24) that monitors the output voltage (Vout); the control unit (10) is provided with an A/D converter (13) that samples a monitored voltage value (Vd) of the voltage detection circuit (24); and a pulse oscillator (14) that controls the position of one edge by an A/D conversion synchronous signal (Ss) indicating the start of sampling by the A/D converter (13), and generates the pulse width modulation signal (Sw), which controls the position of the other edge based on the monitored voltage value (Vd).

Abstract: A semiconductor storage device and method of manufacturing same at a lower cost by without forming a photolithographic resist. Second impurity regions are arranged in such a manner that second impurity regions adjacent along the column direction are joined together. A select gate electrode is arranged into a ring shape so as to surround the second impurity regions, and is electrically connected to a word line. A first control gate electrode is arranged into a ring shape on the outer peripheral side of the select gate electrode, and a second control gate electrode is arranged into a ring shape on the inner peripheral side of the select gate electrode. A pair of first and second bit lines corresponding to every row are placed on the memory cells of the device, a first bit line is electrically connected to one of first impurity regions that are adjacent along the row direction, and a second bit line is electrically connected to the other of the first impurity regions that are adjacent along the row direction.

Abstract: A light receiving circuit includes: a light receiving element that receives an optical signal and converts into an electrical signal; a comparator that demodulates the information on the optical signal to a pulsed signal; a band limit circuit disposed between the light receiving element and the comparator, the band limit circuit removing noise components of frequency higher than the pulsed signal; and a comparator threshold circuit disposed between the light receiving element and the comparator, the comparator threshold circuit generating a threshold of the comparator and limiting the threshold of the comparator within a binary range.

Abstract: An interconnect substrate is placed over a first inductor of a semiconductor chip and a second inductor of another semiconductor chip. The interconnect substrate includes a third inductor and a fourth inductor. The third inductor is located above the first inductor. The distance from the first inductor to the third inductor is longer than the distance from the second inductor to the fourth inductor.

Abstract: A line sensor includes a second conductive type semiconductor substrate where a first conductive type well region is formed, a pixel line formed in the well region, a plurality of pixels being formed on the well region, the plurality of pixels generating charges corresponding to an incident light, a CCD register unit formed on the well region, a transfer electrode being arranged on the well region, the transfer electrode transferring the charges in response to a transfer clock, an output circuit which outputs a voltage signal corresponding to the charges transferred by the transfer electrode, a wiring part which supplies a reference potential to the well region and the output circuit, and a resistor which is included in a wiring, the wiring connecting a first contact between the well region and the wiring part to a second contact between the output circuit and the wiring part.

Abstract: Disclosed is a semiconductor integrated circuit device operated in stability by high-speed clock signals and which is high in a cell using rate and in interconnection efficiency. In a mid part of a chip, there are provided an I/O 11b, supplied with a clock signal from outside, and a PLL 12, connected to the I/O 11b, and adapted for routing an internal clock signal, generated on the basis of the clock signal, to DRAM macros 14. The PLL 12 generates the internal clock signal by multiplying the frequency of the clock signal. The internal clock signal generated is distributed via buffer 13 to each macro cell in need of the internal clock signal. Part of the DRAM macros may be replaced by logic macro cells.

Abstract: A semiconductor device provided on a semiconductor substrate having a cell placing area disposed on a semiconductor substrate, the cell placing area including a plurality of basic cells supplied with power from a local power supply line, a global power supply line to supply power to the local power supply line, at least one switch cell having a terminal electrically connected to the global power supply line, another terminal electrically connected to the local power supply line and a switch to turn on and off power supply from the global power supply line to the local power supply line and a repeater circuit disposed in the cell placing area, the repeater circuit supplied with power from the global power supply line without interposing the switch.

Abstract: In a method for preparing focus-adjustment data for a focusing lens system of an optical defect-inspection apparatus, a wafer having a plurality of defects is positioned in place with respect to a focal plane defined by the focusing lens system at a positioning step, and the detects on the wafer are optically and electronically detected at a detecting step. Then, defects having a predetermined size are extracted among the detected defects at extracting step, and a number of the extracted defects is counted as defect-number data. The positioning, detecting, extracting and counting steps are repeated whenever the focus-adjustment wafer is relatively shifted from the focal plane by a predetermined distance, and a defect-number distribution is produced based on the defect-number data thus obtained.

Abstract: A differential amplifier includes a first differential pair formed by transistors of a first conductivity type, to receive input signals and output first differential-mode currents, a first current amplifier section to output a first output source current and a first output sink current to a first output terminal and a second output terminal, respectively, based on the first differential-mode currents, a second differential pair formed by transistors of a second conductivity type, to receive the input signals and output second differential-mode currents, and a second current amplifier section to output a second output source current and a second output sink current to the first output terminal and the second output terminal, respectively, based on the second differential-mode currents.

Abstract: In the multiple-layered semiconductor device and the method for manufacturing thereof according to the present invention, the resin is formed on the substrate around the semiconductor device, on which the semiconductor device is installed in the first semiconductor package. Therefore, a generation of a warpage of substrate is inhibited in the first semiconductor package. And since the first semiconductor package is stacked to and coupled to the second semiconductor package via the electric conductors that extend from the back surface of the second semiconductor package to the coupling lands on the substrate penetrating through the resin, a defective situation such as a coupling defective in the bump junction can be avoided when the junction of the second semiconductor package via the electric conductor is formed. Therefore, a considerably improved coupling reliability in the multiple-layered semiconductor device can be achieved.

Abstract: A method of forming a multi-layered insulation film includes forming a first insulation layer using a first feed gas, the first insulation layer including methyl silsesquioxane (MSQ), forming a second insulation layer using a second feed gas, the second insulation layer including a polysiloxane compound having an Si—H group such that the second insulation layer is in contact with a top of the first insulation layer, and forming a third insulation layer including an inorganic material such that the third insulation layer is in contact with a top of the second insulation layer.

Abstract: An embodiment of the present invention provides a phase difference detection circuit for detecting a phase difference between input data and an input clock generated based on the input data, including: an input data edge position detecting part detecting an edge position of the input data based on an N-phase clock obtained by dividing a predetermined period into N areas (N is an integer of 2 or more); an input clock edge position detecting part detecting an edge position of the input clock based on the input clock and the N-phase clock; and a phase difference detecting part detecting the phase difference between the input data and the input clock based on the edge position of the input data and an edge position of the input clock.

Abstract: In a semiconductor device including two circuit blocks, an ESD protection circuit between power supply terminals (or ground terminals) of the two circuit blocks having the same voltage level as each other is constructed by at least one diode-connected field effect transistor whose back gate potential is adjusted by a back gate potential adjusting circuit. As a result, the absolute value of the threshold voltage and the ON resistance of the ESD protection circuit can be changed in accordance with whether the operation mode is an ESD protection operation mode or a usual operation mode.

Abstract: A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.

Abstract: A semiconductor device with integrated MIS field-effect transistors includes a first transistor containing a first gate electrode having a composition represented by MAx and a second transistor containing a second gate electrode having a composition represented by MAy, wherein M is at least one metal element selected from the group consisting of W, Mo, Ni, Pt, Ta, Pd, Co and Ti; A is silicon and/or germanium; 0<x?3 and 0<y?3, and x and y are different from each other.

Abstract: The semiconductor device includes a substrate over one surface of which an electroless plating electrode film is formed; a semiconductor chip mounted over the one surface of the substrate; and a bonding wire which connects the semiconductor chip and one surface of the electroless plating electrode film, a recessed depth which is a difference between a lowermost height of a bonding portion of the one surface of the electroless plating electrode film to the bonding wire, and an uppermost height of the one surface other than the bonding portion being equal to or less than 1.5 ?m.

Abstract: A bipolar transistor at least includes a semiconductor substrate including an N? epitaxial growth layer and a P? silicon substrate, an N+ polysilicon layer, a tungsten layer, two silicide layers, a base electrode, an emitter electrode, and a collector electrode. The N+ polysilicon layer formed on the semiconductor substrate is covered with one of the silicide layers. The tungsten layer that is formed on the silicide layer is covered with the other silicide layer.