Abstract: A semiconductor device of improved stress-migration resistance and reliability includes an insulating film having formed therein a lower interconnection consisting of a barrier metal film and a copper-silver alloy film, on which is then formed an interlayer insulating film. In the interlayer insulating film is formed an upper interconnection consisting of a barrier metal film and a copper-silver alloy film. The lower and the upper interconnections are made of a copper-silver alloy which contains silver in an amount more than a solid solution limit of silver to copper.

Abstract: Disclosed is a frequency divider including first to fifth FFs(flip-flops), each of which receives a common clock signal and samples and outputs an input signal responsive to an effective edge of the clock, an output signal of the 1st FF being supplied to the 2nd FF, a first logic gate which receives an output signal of the 2nd FF and a first control signal and outputs the output signal of the 2nd FF, when the first control signal is of a first value, and outputs a predetermined value, when the first control signal is of a second value, the output signal of the first logic gate being supplied to an input of the 3rd FF; a second logic gate which receives an output signal of the 1st FF and a second control signal and outputs an output signal of the 1st FF, when the second control signal is of the first value and outputs the predetermined value, when the second control signal is of the second value, the output signal of the second logic gate being supplied to the 4th FF; and a third logic gate which receives an o

Abstract: A symbol timing detection method, executed in a processor, is provided where, upon detecting a symbol timing from a received signal composed of a packet having a preamble with periodically allocated symbols placed at a head of data, correlation results indicating a correlation between the received signal and a fixed pattern of the preamble are obtained, a maximum value in the correlation results are updated and held, and a timing of the maximum value is determined as a symbol timing on a condition that a maximum value currently held by the correlation peak detection unit is not updated in a symbol timing determination period having a predetermined length from the timing and that a number of occurrences of a correlation result exceeding an error detection determination threshold is smaller than a predetermined number in an error detection determination period defined within the symbol timing determination period.

Abstract: Disclosed is a semiconductor storage device comprising a semiconductor substrate, a first and a second impurity diffusion layer formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on the semiconductor substrate via the gate insulating film. The gate insulating film has a nitrogen-containing silicon oxide film inside, and a silicon oxide film is so arranged on both sides of the nitrogen-containing silicon oxide film as to sandwich the nitrogen-containing silicon oxide film. In addition, the nitrogen composition in the nitrogen-containing silicon oxide film is increased from the semiconductor substrate side to the first gate electrode side.

Abstract: A semiconductor device includes a lower electrode provided on a semiconductor substrate, an upper electrode provided on the lower electrode to overlap a part of the lower electrode, a first insulating film provided between the lower electrode and the upper electrode, and a second insulating film provided in contact with an upper part of the upper electrode and on the upper part of the lower electrode, and having a density higher than that of the first insulating film, the second insulating film covering a side surface and a top surface of the upper electrode.

Abstract: To provide a retainer ring by which an object to be polished can be uniformly polished, and deterioration thereof can be suppressed, and it does not take time to recycle, and a polishing machine having the retainer ring. The retainer ring 1 includes: a first annular portion 11 for surrounding an outer circumferential portion of the object to be polished and made of resin; and a second annular portion 12 provided on the first annular portion 11 and having a mechanical strength higher than that of the first annular portion 11. In rim portions of the first annular portion 11 and the second annular portion 12, a fixing portion 13 for fixing the first annular portion 11 and the second annular portion 12 with mechanical joining is provided. The first annular portion 11 protrudes beyond the fixing portion 13 toward the opposite side of the second annular portion 12.

Abstract: A method of manufacturing a semiconductor apparatus includes forming an electrode on a semiconductor device, forming a conductive bump on the electrode, placing an external wire on the conductive bump, and laser-welding the external wire and the conductive bump to establish electrical connection.

Abstract: A semiconductor laser element realizes a high COD light output in broader range of reflection factor at a facet with high reliability. A semiconductor laser element has a multi-layered reflection film formed on at least one end facet of a resonator. An optical path length of each layer of said multi-layered reflection film is determined by (2m?1)·?/4, where ? is oscillation wavelength, and m is positive integer). A high-refractive-index layer and a low-refractive-index layer are alternately stacked starting from a first layer adjacent to said semiconductor.

Abstract: A semiconductor device on a tape carrier package with improved heat dissipation, as provided. The number of outputs of the semiconductor device has been increased for implementing a multi-channel configuration, and narrower pitches are employed. Included are a tape carrier 20 having lead patterns 21 to 24 formed on a tape base 28 thereof, and a semiconductor device 10 mounted on the tape carrier 20 and having electrode patterns 11 to 14 disposed thereon. The semiconductor device 10 includes heat dissipating electrode patterns 15 to 17 at positions where the heat dissipating electrode patterns 15 to 17 do not interfere with the electrode patterns 11 to 14. The lead patterns 21 to 24 are electrically connected to the corresponding electrode patterns 11 to 14, respectively. On the tape carrier 20, heat dissipation patterns 25 to 27 are formed. The heat dissipation patterns have a surface area broader than that of the lead patterns and have the heat dissipating electrode patterns disposed thereon.

Abstract: The present invention is aimed at realizing an amplifying circuit whose chip size is prevented from being significantly increased even if the number of compatible frequencies increases, and which has a wide dynamic range when it operates under a low voltage.

Abstract: A heterojunction bipolar transistor includes a first conductivity type subcollector layer, a first collector layer containing a first conductivity type impurity, a third collector layer containing a higher concentration of the first conductivity type impurity than the first collector layer, a second collector layer containing a lower concentration of the first conductivity type impurity than the first collector layer, a second conductivity type base layer, a first conductivity type emitter layer containing a semiconductor with a wider bandgap than the base layer, and a first conductivity type emitter cap layer.

Abstract: Conventional semiconductor memory devices have a problem of a data read failure caused by a leak current. To address this problem, a semiconductor memory device of the present invention including memory cells each formed of a transfer transistor, a load transistor and a drive transistor. Each of the memory cells includes: a first transfer transistor connected to a connection point of the drive transistor and the load transistor; a second transfer transistor connected between the first transfer transistor and a bit line DB; and a compensation transistor connected between a constant voltage node and a connection point of the first transfer transistor and the second transfer transistor. The compensation transistor is switched to a conductive state exclusively from at least one of the first transfer transistor and the second transfer transistor.

Abstract: One exemplary embodiment includes a difference image generation device including a measurement unit and a scaling unit. The measurement unit measures a variation width of pixel values of a difference image signal obtained by performing subtraction processing on first and second input image signals. The scaling unit scales each pixel value of the difference image signal based on a measurement result of the variation width so that the difference image signal can be represented in grayscale using a predetermined bit width, and outputs a difference image signal subjected to scaling.

Abstract: A circuit for detecting variation of a resistance value of a resistor with respect to a reference value includes a first resistor; a second resistor; a first current source circuit for supplying current to the first resistor; a second current source circuit for supplying current to the second resistor; a voltage comparator circuit for comparing a voltage across the first resistor and a voltage across the second resistor; and a control circuit for digitally adjusting the supply current of at least one of the first or second current source circuit. A ratio of resistance values of the first and second resistors can be obtained from an adjustment value from the control circuit and result of comparison from the voltage comparator circuit.

Abstract: An operational amplifier includes an input differential stage having one external input receiving an external input voltage and two outputs; and two output stages. A switch section is provided between inputs of the two output stages and the two outputs of the input differential stage, and is configured to alternately connect the two outputs of the input differential stage and inputs of a positive-only output stage of the two output stages; and the two outputs of the input differential stage and inputs of a negative-only output stage of the two output stages.

Abstract: A power supply circuit for a display apparatus, includes: a voltage boosting circuit configured to boost up an input voltage based on a voltage boosting factor to output a boosted output voltage; a voltage detecting circuit configured to compare a voltage level of a power supply voltage to which the input voltage is related and a predetermined voltage level; and a control circuit configured to output one of a first voltage boosting factor and a second voltage boosting factor as the voltage boosting factor to the voltage boosting circuit based on the comparison result. The control circuit changes the voltage boosting factor during a blanking period in a display panel.

Abstract: There is provided a PLL circuit including a first loop filter and a second loop filter, which includes a current signal generation circuit that includes a first output driver that generates a first current signal to be output to the first loop filter and a second output driver that generates a second current signal to be output to the second loop filter, and a control circuit that selects which of the first output driver and the second output driver is to be activated.

Abstract: A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance.

Abstract: A driver includes a gradation voltage supplying section configured to supply a first output gradation voltage to a data line in a first display period; and a charge share performing section configured to supply a second voltage between the first output gradation voltage and a first voltage to the data line in a charge share period after the first display period. The first voltage is a common voltage between the first output gradation voltage and a second output gradation voltage of a polarity opposite to that of the first output gradation voltage.

Abstract: A semiconductor memory device includes (a) a plurality of reference cells, (b) a plurality of memory cells, data stored in a selected reference cell among the reference cells being compared to data stored in a selected memory cell among the memory cells, (c) an address transition detector for detecting transition in input of addresses by which a memory cell is selected among the memory cells, and transmitting an address transition detecting signal indicative of the detected transition, (d) a counter for counting the address transition detecting signals, and (e) a reference cell decoder for selecting a reference cell among the reference cells in accordance with an output transmitted from the counter.