Abstract: Additional transistors P1 and P2 which are PMOS transistors are connected to load transistors PL1 and PL2 which are PMOS transistors such that drain electrodes of the additional transistors P1 and P2 and drain electrodes of the load transistors PL1 and PL2 are connected at a node 1 and a node 2 while gate electrodes of the additional transistors P1 and P2 and gate electrodes of the load transistors PL1 and PL2 are connected at the node 1 and the node 2. A source electrode of the additional transistor P1 is connected to an additional transistor control circuit, which is provided for each column. The additional transistor control circuit sets control signals S1 and S2 to the H level in other times than data write so that the additional transistor P1 or P2 compensates the load transistor PL1 or PL2, thereby increasing the static margin.

Abstract: A semiconductor device includes: a semiconductor substrate; a semiconductor element formed on a principal surface of the semiconductor substrate and having a multiple-layered interconnect layer; and a heterostructure magnetic shield covering the semiconductor element. The heterostructure magnetic shield includes a first magnetic shield layered structure and a second magnetic shield layered structure that covers the first magnetic shield layered structure. Each of a first and a second magnetic shield layered structures includes a magnetic shielding film composed of a magnetic substance and covering the semiconductor element and a buffer film disposed between the semiconductor element and the magnetic shield films and preventing a diffusion of the magnetic substance.

Abstract: A combination includes a first bus master coupled to a first bus to output a first signal group including at least one of signals onto the first bus, a second bus master coupled to the first bus to output a second signal group including at least one of signals onto the first bus, an interconnect section coupled between the first bus and a second bus to receive the first and second signal groups and to output a third signal group including at least one of signals onto the second bus, and a bridge section coupled between the second bus and a third bus to receive the third signal group and to output a fourth signal group including at least one of signals onto the third bus free from performing a selecting operation for the third signal group.

Abstract: An input stage of a differential amplifier includes a differential pair formed by an N-channel MOS transistor MN1 having a gate connected to an INM and an N-channel MOS transistor MN2 having a gate connected to an INP, both having sources connected to each other, a constant current source connected to the sources of the MN1 and MN2, and a variable current source connected to the sources of the MN1 and MN2. A subsequent-stage processing circuit having an intermediate stage and an output stage includes a phase compensation capacitor and outputs an output responsive to a change in the differential inputs by charging and discharging the phase compensation capacitor through the constant current source. The variable current source turns ON when the change reaches a level causing a parasitic capacitor at the sources of the differential pair to be discharged, and supplies a current for discharging the parasitic capacitor.

Abstract: A semiconductor device includes a semiconductor substrate and an alignment mark. The alignment mark is provided on the semiconductor substrate and optically detectable. The alignment mark includes a bright area and a dark area. The bright area outputs light reflected from a surface of the semiconductor substrate. The dark area includes metal wirings, outputs light reflected from surfaces of the metal wirings, and has brightness lower than that of the bright area.

Abstract: The present invention provides a super-junction semiconductor element having a high voltage resistance and a low resistivity, while being successfully reduced in the size thereof, which comprises a semiconductor substrate 3; a pair of electrodes 1, 2 provided respectively on a top surface 12 and a back surface 13 of the semiconductor substrate 3; a parallel pn layer provided between the top surface 12 and the back surface 13 of said semiconductor substrate, having n-type semiconductor layers 4 allowing current flow under the ON state but being depleted under the OFF state, and p-type semiconductor layers 5 alternately arranged therein; and an insulating film 6 formed so as to surround the parallel pn layer; wherein the insulating film 6 is formed at a predetermined position.

Abstract: A semiconductor memory device includes a first well region of a first conductivity type, first and second SRAM cells adjacently arranged to each other, the first and second SRAM cells each including at least a first transfer transistor and a drive transistor formed on the first well, the first transfer transistor and the drive transistor being coupled in series between a bit line and a power source line, and a first diffusion region of the first conductivity type arranged between the drive transistor of the first SRAM cell and the drive transistor of the second SRAM cell, to apply a first well potential to the first well.

Abstract: A communication system carrying out an isochronous transfer, includes a cycle master node and nodes connected with each other through a system bus. The cycle master node sets a cycle time of the isochronous transfer and transfers a cycle start packet onto the system bus for every the cycle time. Each of the nodes transfers an isochronous packet onto the system bus in response to the cycle start packet.

Abstract: A DQS detection circuit 13 detects a preamble of a DQS signal outputted from RAM 11. An up/down counter 14 counts up a number of clock signals CLK) in a period when an DQSEIN signal showing a continuation length of the DQS signal is active, counts down a number of trailing edges of the DQS signal after the preamble corresponding to a data read request, and detects that a counted value is set to 0. A flip-flop circuit FF2 makes a mask signal MS) a low level when the counted value is set to 0. An AND circuit AND2 makes the DQS signal maskable with a mask signal MS.

Abstract: The present invention solves a problem of the degradation of the long-term reliability of a conventional semiconductor memory device due to early deterioration of a FET included in a reference cell therein. DRAM 1 has word lines 101 to 10n, word lines 22 and 24, memory cells 301 to 30n and a reference cell 40. Gates of FETs 32 in the memory cells 301 to 30n are connected to the word lines 101 to 10n respectively. Gates of a FET 42 and a FET 44 in the reference cell 40 are connected to the word line 22 for readout and the word line 24 for writing respectively. Here, potentials applied to the word lines 22 and 24 are lower than those applied to the word lines 101 to 10n.

Abstract: A semiconductor device, includes a package substrate having a first surface and a second surface opposite to the first surface, and a semiconductor element installed in the first surface of the package substrate. The package substrate includes a plurality of first land pads disposed in the first surface, second land pads disposed in the second surface and a second testing-dedicated pad disposed in the second surface.

Abstract: When a manufacturing process becomes finer and a threshold value drops, a leakage current generates in a MOS transistor that is normally in an off-state. In order to suppress an influence of a leakage current that is generated in a protection transistor that constitutes a protection circuit on the internal circuit, an adjustor circuit that forms a transit path of the leakage current is disposed within the protection circuit, and a monitor circuit having the same circuit configuration as a configuration of the protection circuit is disposed to control an impedance of the transit path in the protection circuit and the monitor circuit so as to allow the leakage current to flow through the transit path.

Abstract: Failure analysis method includes performing fixed radiation of semiconductor chip (wafer) by photocurrent generation laser beam, scanning and radiating a region to be observed on semiconductor chip by heating laser beam, detecting, by a SQUID fluxmeter, current change generated in the semiconductor chip by radiating the photocurrent generation laser beam and the heating laser beam, and analyzing failure of the semiconductor chip based on current change detected by the SQUID fluxmeter. Radiation of photocurrent generation laser beam and heating laser beam are performed from a back surface side of the LSI chip, and detection by the SQUID fluxmeter is performed on a front surface side of the LSI chip. In analysis of failure of the LSI chip, image processing is performed in which a signal outputted from the SQUID fluxmeter is made to correspond to a scanning point. Visualization of defects is possible.

Abstract: A communication message conversion device according to the present invention comprises a first receiving unit receiving a first message according to a first communication protocol, a first message storage unit storing the first message received by the first receiving unit in one of a plurality of buffer areas according to a first message identifier contained in the first message, a first identifier conversion unit converting the first message identifier contained in the first message stored in the first message storage unit into a second message identifier, a first message conversion unit packing a plurality of first messages converted with the first identifier conversion unit into a second message and a first transmission unit transmitting the second message converted with the first message conversion unit according to a second communication protocol.

Abstract: A reset signal generating circuit outputs a reset signal having a sufficient pulse width even when the power supply voltage is fluctuated. A node B reaches a high level during a power-on reset and is at a low level during operation. When a power supply (Vcc) fluctuates during operation and as soon as a node C reaches a high level, a switch element MN50 turns on, the node B is decreased to a low level, and a stable low-level reset signal RST1 is outputted. When the node B reaches a low level, a switch element MN51 turns off with a delay and capacitors 104 and 105 are gradually charged by a charging circuit 112. When the potential at the node B exceeds a threshold level of an inverter circuit 106, the reset signal RST1 is brought back to a high level, the reset is cancelled, the switch element MN50 is turned off, and the switch element MN51 is brought to be in an on-state again (FIG. 1).

Abstract: A semiconductor memory device (1) has a FET (10) (first field-effect transistor), a FET (20) (second field-effect transistor), a contact plug (32) (first conductive plug), contact plugs (34) (second conductive plugs), and a detection circuit (50). The FET (20) is provided in a double well (40). M (m is a natural number) contact plugs (32) are connected to a diffusion layer (22) of the FET (20) while n (n is a natural number) contact plugs (34) are connected to a diffusion layer (24). Here, m is smaller than n. The detection circuit (50) detects the difference between the output of the FET (10) and the output of the FET (20).

Abstract: Class D amplifier is resistant to interferences. Binary output signals y1 and y2, are generated from input signal s1, delivered to input terminal IN, to drive a load connected across output terminals OUTP and OUTN. Pulse generating circuit 10 generates a pulse width modulated pulse signal y0 from input signal s1, inverted signal of the output signal y1 and output signal y2. Differential pulse generating circuit 14 receives pulse signal y0 and inverts low and high levels of pulse signal y0, while shifting the resulting signal by half period from the pulse signal y0, to generate a pulse signal y3. Pulse amplifier 11a receives pulse signal y0 and generates output signal y1 supplied to output terminal OUTP. Pulse amplifier 11b receives pulse signal y3 and generates output signal y2 delivered to output terminal OUTN.

Abstract: An interconnect is provided in a first insulating layer and the upper surface of the interconnect is higher than the upper surface of the first insulating layer. An air gap is disposed between the interconnect and the first insulating layer. An etching stopper film is formed over the first insulating layer, the air gap, and the interconnect. A second insulating layer is formed over the etching stopper film. A via is provided in the second insulating layer and is connected to the interconnect. A portion of the etching stopper film that is disposed over the air gap is thicker than another portion that is disposed over the interconnect.

Abstract: A light receiving circuit in accordance with an exemplary aspect of the present invention includes a photodiode 6 that converts an optical input signal into a current signal, and an I-V conversion circuit 8 that converts the current signal into a voltage signal. The light receiving circuit further includes a transient current processing circuit 21 that process a transient current from the I-V conversion amplifier 8 when the I-V conversion amplifier 8 is changed from an operating state to a non-operating state, and a clipping circuit 24 that keeps the voltage of the input terminal of the transient current processing circuit 21 at a predetermined value.

Abstract: A display driver includes a gradation data register that stores gradation data having a bit width, and a gradation voltage signal generator that generates a gradation voltage signal that has voltage according to the gradation data stored in the gradation data register and outputs the generated gradation voltage signal, the display driver further including a test circuit that is provided between the gradation data register and the gradation voltage signal generator, the test circuit connecting at least a plurality of bit lines among bit lines provided between both of the circuits through a common node in a test mode, so as to perform failure detection based on a value of current that flows in the common node.