Patents Assigned to NEC Electronics
  • RECEIVER AND METHOD OF REDUCING OPERATING CURRENT THEREOF
    Publication number: 20090325525
    Abstract: Disclosed is a receiver so adapted that even it receives a signal having the same communication frequency and frequency band as its own, restart of a receive-signal processor is inhibited for a fixed period of time if the receive signal is not a desired signal. The result is a reduction in power consumption. The receiver includes a start circuit for detecting a radio-frequency signal and outputting a start signal if a level of the detected radio-frequency signal is no less than a fixed level, and a receive-signal processor for receiving the start signal and starting a demodulating operation for demodulating the radio-frequency signal.
    Type: Application
    Filed: June 25, 2009
    Publication date: December 31, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Tatsuhiko MARUYAMA
  • PROCESS FOR MANUFACTURING SEMICONDUCTOR DEVICE
    Publication number: 20090325104
    Abstract: An operation for forming a trench after forming a via hole includes an operation for exposing a region for forming the via hole to light and an operation for exposing a region for forming the interconnect trench. More specifically, even if chemically amplified resist is buried in the via hole after the via hole is formed, then the region for forming of via hole is exposed to light again, so that the inside of the via hole is fully exposed to light. This allows removing the buried resist from the regions in via hole exposed to light, or namely the region and the region, with a developing solution, exposing at least a portion of the inner wall of the via hole to obtain the trench having a desired structure.
    Type: Application
    Filed: June 25, 2009
    Publication date: December 31, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Fumiaki Hayashi
  • Semiconductor integrated circuit apparatus and control method thereof
    Patent number: 7640473
    Abstract: A semiconductor integrated circuit apparatus includes an internal logic circuit unit, a first memory, a second memory and a control circuit unit. The internal logic circuit unit includes scan chains which test circuit normality. The first memory is accessed by the internal logic circuit. The second memory stores valid bits associated with the first memory, wherein the valid bits indicates one of validity and invalidity of data stored in the first memory. The control circuit unit saves internal state data stored in the scan chains to the first memory, and resets the internal state data saved in the first memory to the scan chains.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: December 29, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Tatsuya Kawasaki
  • Method for inspecting mask
    Patent number: 7640530
    Abstract: A mask inspection system 10 inspects an inspection object pattern while comparing an inspection object data obtained in such a way as to image the inspection object pattern with a reference pattern data. The mask inspection system 10 is provided with an inspection information preparing part 12 producing inspection algorithm and inspection sensitivity to the reference pattern data based on wafer simulation, a converting part 13 generating a reference graphic data with inspection information while adding the inspection information to the reference graphic data, and a defect judging part 16 judges propriety of an inspection object pattern data while comparing reference graphic data with an inspection object data in every pixel based on the inspection information added to the reference graphic data with inspection information.
    Type: Grant
    Filed: December 27, 2004
    Date of Patent: December 29, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Akihiko Ando
  • Differential amplifier and data driver employing the differential amplifier
    Patent number: 7639167
    Abstract: Disclosed is a differential amplifier which includes first and second input terminals, an output terminal, first and second differential pairs, and first and second current sources for supplying currents to the first and second differential pairs. The first differential pair has first and second inputs of an input pair connected to the first input terminal and the output terminal, respectively. The second differential pair has first and second inputs of an input pair connected to the second input terminal the output terminal, respectively.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: December 29, 2009
    Assignees: NEC Corporation, NEC Electronics Corporation
    Inventor: Hiroshi Tsuchi
  • Integrated circuit incorporating decoupling capacitor under power and ground lines
    Patent number: 7638821
    Abstract: A semiconductor device is composed of: an array of CMOS primitive cells provided in a circuit region; a power supply line extended along the array of the CMOS primitive cells and connected to the CMOS primitive cells; a ground line extended along the array of the CMOS primitive cells and connected to the CMOS primitive cells; a first decoupling capacitor provided under the power supply line; a second decoupling capacitor provided under the ground line. The first decoupling capacitor is formed of a PMOS transistor having a gate connected to the ground line. At least one of the source and drain of the PMOS transistor is connected to the power supply line. The second decoupling capacitor is formed of an NMOS transistor having a gate connected to the power supply line. At least one of the source and drain of the NMOS transistor is connected to the ground line.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: December 29, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Yasushi Aoki
  • Semiconductor device and method of testing semiconductor device
    Patent number: 7639554
    Abstract: A semiconductor device includes: a first memory; and a second memory. The first memory includes: a first memory cell array configured to be divided into a plurality of sectors, an erasure time setting register configured to hold a sector erasure assurance time to assure an erasure time for erasing data stored in one sector, and a first control circuit configured to execute a sector erasure test in which data stored in at least one selected sector selected from the plurality of sectors are erased within the sector erasure assurance time. The second memory includes: a second memory cell array configured to have a data storage system different from that of the first memory cell array, and a second control circuit configured to execute a data hold test with respect to the second memory cell array while the sector erasure test is executed.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: December 29, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Kiyokazu Hashimoto, Nobutoshi Tsunesada
  • Semiconductor device having separated drain regions
    Patent number: 7638849
    Abstract: A semiconductor device according to an embodiment of the invention includes: a plurality of field effect transistors; and a plurality of logic circuits composed of the field effect transistors, the field effect transistors each including: first and second drain regions formed away from each other; at least one source region formed between the first and second drain regions; and a plurality of gate electrodes formed between the first drain region and the source region and between the second drain region and the source region.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: December 29, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Hiroshi Furuta, Hiroyuki Takahashi
  • Semiconductor chip and method of fabricating the same
    Patent number: 7638369
    Abstract: There is provided a semiconductor chip having fuses. The semiconductor chip includes fuses each having a first terminal electrically connected to a first logic circuit, a second terminal electrically connected to a second logic circuit, and a blowable region formed between the first terminal and the second terminal; and fuse residues each having the same patterns with those of the first terminal and the second terminal of the fuses, and configured so that patterns corresponded to the first terminals and the second terminals are electrically disconnected from each other.
    Type: Grant
    Filed: February 3, 2006
    Date of Patent: December 29, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Takashi Sakoh, Ryo Kubota
  • Program creation apparatus, program creation method and program
    Patent number: 7640509
    Abstract: A program creation apparatus creates a program for a microcomputer that includes an input section, a processor and an output section. The apparatus includes a GUI display section displaying a plurality of icons, each corresponding to each operation of the input section, the processor and the output section, and a program creator creating a program according to manipulation of the icons by a user.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: December 29, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Takahisa Gunji, Tatsuya Maeda
  • Error detecting code calculation circuit, error detecting code calculation method, and recording apparatus
    Patent number: 7640483
    Abstract: The recording apparatus adds EDC to user data and transfers the EDC-added data to the scrambler in a sequence different from the coding direction Q. Though the processing data is added at an end in the direction Q, it is inserted at middle in the different sequence. Therefore, in order to transfer the EDC-added data in the different sequence, the EDC generator calculates an EDC intermediate value from an expected value of a latter part of an even number sector. Then, the EDC generator receives the user data in the different sequence and calculates EDC from expected values of the first half of the even number sector and an odd number sector and the EDC intermediate value. The expected value is an error detecting value of code string that has the same number of bits as the EDC-added data and a corresponding bit in the sequence of the direction Q is 1 and other bits are 0.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: December 29, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Takeo Ariyama
  • Teaching device and teaching method
    Publication number: 20090319216
    Abstract: Teaching of height of a carrier stage relative to a transfer arm is performed with high accuracy. A teaching device is used when teaching the height of a carrier stage 5 relative to a transfer arm 4 in a transfer system is performed. The transfer system includes the transfer arm 4 that transfers a wafer and the carrier stage 5 with a carrier 1 that holds the wafer mounted thereon. The teaching device includes a teaching jig 10 and a detector 20. The teaching jig 10 includes a disc 11 arranged on a slot base 2 in the carrier 1 and a head member 12 attached to the disc. The head member 12 has a projecting portion designed to be located within an optimal gap between the disc 11 and the transfer arm 4 disposed below the disc 11.
    Type: Application
    Filed: June 10, 2009
    Publication date: December 24, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Taketora Ogata
  • ANALYSIS AND DESIGN APPARATUS FOR SEMICONDUCTOR DEVICE AND ANALYSIS AND DESIGN METHOD FOR SEMICONDUCTOR DEVICE
    Publication number: 20090319967
    Abstract: An analysis and design apparatus for semiconductor device, includes a storage portion, a parameter setting portion, an element characteristic calculation portion, and a determination portion. The storage portion stores structure information and measured values of a transistor. The parameter setting portion divides a channel region into a plurality of regions, and temporarily sets a plurality of impurity concentrations for the plurality of regions as a plurality of parameters. The element characteristic calculation portion calculates a plurality of effective impurity concentrations in the plurality of regions based on the plurality of parameters, calculates a surface potential by solving a Poisson equation using the plurality of effective impurity concentrations, and calculates calculated values of electric characteristics of the transistor using the surface potential.
    Type: Application
    Filed: June 10, 2009
    Publication date: December 24, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Hironori Sakamoto
  • Semiconductor integrated circuit
    Publication number: 20090315191
    Abstract: In order to form a semiconductor integrated circuit capable of effectively using a chip area, there is provided a semiconductor integrated circuit (1) including: a plurality of bonding pads (5, 6, 7) formed along an edge of a semiconductor substrate (2); a plurality of I/O cells (3) arranged along the edge under the plurality of bonding pads (5, 6, 7); an upper layer wire mesh (24) including a plurality of upper layer wirings (13); and a core region (4) formed on the semiconductor substrate (2). In the semiconductor integrated circuit (1), the core region (4) has an area larger than an area occupied by the upper layer wire mesh (24) in a plane parallel to a surface of the semiconductor substrate (2).
    Type: Application
    Filed: April 9, 2009
    Publication date: December 24, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Kenichi Ishikawa
  • Reconfigurable device
    Publication number: 20090319754
    Abstract: A reconfigurable device comprises a plurality of processing elements, a main memory unit that stores plural pieces of circuit configuration information, a cache unit that caches circuit configuration information forwarded to at least one of the processing elements from the main memory unit, and a cache control unit that controls forwarding of circuit configuration information from the cache unit to the processing element. The cache control unit selects circuit configuration information which must be forwarded to each processing element. When the selected circuit configuration information is not stored in the cache unit, the cache control unit reads out the circuit configuration information from the main memory unit, stores the read-out circuit configuration information in the cache unit, and sends forward the circuit configuration information to the processing element from the cache unit.
    Type: Application
    Filed: June 17, 2009
    Publication date: December 24, 2009
    Applicants: NEC Corporation, NEC Electronics Corporation
    Inventors: Takao TOI, Toru AWASHIMA, Taro FUJII, Toshiro KITAOKA, Koichiro FURUTA, Masato MOTOMURA
  • Method for manufacturing semiconductor device and the semiconductor device
    Publication number: 20090315186
    Abstract: An etching stopper film is formed on top of a first insulating film. The etching stopper film is a film formed by depositing at least two films, made of constituent materials identical in quality to each other, one another. Subsequently, a first opening pattern is formed in the etching stopper film. Subsequently, a second insulating film is formed on top of the etching stopper film. Subsequently, a mask pattern is formed on top of the second insulating film. Subsequently, the second insulating film is etched with the use of the mask pattern as a mask to be followed by etching of the first insulating film with the use of the etching stopper film as a mask.
    Type: Application
    Filed: June 2, 2009
    Publication date: December 24, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Ken Ozawa
  • Semiconductor integrated circuit device, and debugging system and method for the semiconductor integrated circuit device
    Patent number: 7636870
    Abstract: To provide a debugging system, debugging method, and a semiconductor integrated circuit device capable of collecting debug-target information with accuracy and improving debug efficiency. A semiconductor integrated circuit device according to an embodiment of the present invention includes: subsystems; a break detecting unit detecting that a program execution of a CPU core in one subsystem satisfies a predetermined break condition; and a break selecting unit stopping operations of one selected from the subsystems in accordance with the detection result of the break detecting unit.
    Type: Grant
    Filed: October 26, 2006
    Date of Patent: December 22, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Shigeyuki Ueno
  • Wireless ad-hoc communication system and communication terminal synchronizing method in wireless ad-hoc communication system
    Patent number: 7636343
    Abstract: In a wireless ad-hoc communication system according to an embodiment of the invention, a plurality of communication terminals transmit/receive beacons and are synchronized. The wireless ad-hoc communication system includes first and second networks each including one or more communication terminals; and one or more synchronizing terminals. The synchronizing terminals are capable of transmitting/receiving the beacons to/from the communication terminals. In the wireless ad-hoc communication system, at least one of the communication terminals belonging to the first network and at least one of the communication terminals belonging to the second network exist within a reachable range of the beacons from one of the one or more synchronizing terminals to construct one synchronized network with the first network, the second network, and the synchronizing terminals.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: December 22, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Nobuyuki Mizukoshi
  • Semiconductor device with electric fuse having a flowing-out region
    Patent number: 7635907
    Abstract: A semiconductor device includes an electric fuse formed on a semiconductor substrate and composed of an electric conductor. The electric fuse includes an upper layer interconnect, a via coupled to the upper interconnect and a lower layer interconnect coupled to the via, which are formed in different layers, respectively, in a condition before cutting the electric fuse, and wherein the electric fuse includes a flowing-out region formed of the electric conductor being flowed toward outside from the second interconnect and a void region formed between the first interconnect and the via or in the via, in a condition after cutting the electric fuse.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: December 22, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Takehiro Ueda
  • Method and apparatus for detecting abnormal characteristic values capable of suppressing detection of normal characteristic values
    Patent number: 7636609
    Abstract: In a method for detecting abnormal characteristic values of a plurality of products sequentially manufactured in the same manufacturing line, it is determined whether or not a successive-decrease (or increase) tendency has occurred in a plurality of sequentially-obtained characteristic values of the products. Also, it is determined whether or not at least a last one of the characteristic values is located within a control region narrower than an allowable region and outside a normal region narrower than the control region. Further, when the successive-decrease or increase tendency has occurred and the last characteristic value is located within the control region outside the normal region, an alarm state is detected.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: December 22, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Masanobu Higashide