Patents Assigned to NEC Electronics
  • Patent number: 7580282
    Abstract: A floating-gate non-volatile memory is composed of a plurality of banks, and a negative bias power line providing a negative bias for the plurality of banks. Each of the plurality of banks includes a plurality of sectors arranged in columns, each comprising a plurality of floating-gate memory cells; a plurality of column decoders associated with the columns of the sectors, respectively; and a bank decoder connected to the plurality of column decoders through an in-bank power line. A bank decoder within selected one of the banks provides the negative bias received from the negative bias power line for the in-bank power line. Each of the column decoders is responsive to selection/non-selection of associated one of the columns of the sectors for generating a negative voltage signal from the negative bias received from the in-bank power line, and providing the negative voltage signal for the associated one of the columns of the sectors.
    Type: Grant
    Filed: July 26, 2005
    Date of Patent: August 25, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Kazuo Watanabe
  • Patent number: 7579211
    Abstract: A flip-chip type semiconductor device includes a semiconductor chip having electrode pads formed and arranged on a chip surface thereof. Sprout-shaped metal bumps are bonded to the electrode pads on the chip, and an adhesive resin layer is formed on the chip surface of the chip such that tip ends of the sprout-shaped metal bumps are protruded from the adhesive resin layer. A circumference of the tip end of each sprout-shaped metal bump is surrounded by a protective resin material integrally swelled from the adhesive rein layer such that a tip end face of each sprout-shaped metal bump is at least exposed to the outside.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: August 25, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Rieka Ohuchi
  • Patent number: 7579911
    Abstract: An amplifier includes differential output and input stages. The differential output stage includes first and second current paths outputting differential signals and connected between first and second power supplies. The first current path includes a first resistance between the first power supply and a first node, first and second transistors between the first node and a second node, and a second resistance between the second node and the second power supply. The second current path includes a third resistance between the first power supply and a third node, third and fourth transistors between the third node and a fourth node, and a fourth resistance between the fourth node and the second power supply. Each gate of the first to fourth transistors is connected to each of the fourth to first nodes, respectively, and output current of the differential input stage is connected to the first and third nodes.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: August 25, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Yasufumi Suzuki
  • Patent number: 7580134
    Abstract: This invention provides a method and an apparatus of measuring a micro-structure, capable of evaluating a geometry of a micro-structure formed typically on the surface of a semiconductor substrate, in a non-destructive, easy, precise and quantitative manner. A reflection spectrum of a sample having a known dimension of a target micro-geometry is measured (A1), features (waveform parameters) which strongly correlate to a dimension of the measured micro-geometry are determined (A2), a relation between the dimension of the micro-geometry and the waveform parameters is found (A3), and a dimension of the micro-structure having an unknown dimension is finally determined using this relation and based on the reflection spectrum obtained therefrom (A4, A5).
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: August 25, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Yoshiharu Muroya
  • Patent number: 7579996
    Abstract: The present invention provides a small, thin, and cheap foldable broadband antenna that is valid in a wide band and, moreover, can be manufactured at low cost, and a method of using the same. A foldable broadband antenna includes: a plate conductor having a rectangular outer shape and in which a slit is formed from a long side so as be orthogonal to a longitudinal direction; a side conductor provided perpendicularly from a side parallel with the slit in the plate conductor; and a back conductor disposed in parallel with the plate conductor from an end of the side conductor toward the slit. In the plate conductor, a coaxial external conductor of a coaxial cable is connected to the side opposite to the side conductor with the slit therebetween, and a coaxial central conductor of the coaxial cable is electrically connected to the same side as that of the side conductor.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: August 25, 2009
    Assignees: NEC Corporation, NEC Electronics Corporation
    Inventors: Akio Kuramoto, Takuji Mochizuki
  • Patent number: 7579673
    Abstract: A semiconductor device includes a semiconductor substrate, and an electrical fuse provided on the semiconductor substrate. The electrical fuse includes a first fuse link and a second fuse link mutually connected in series, a first current inlet/outlet terminal (first terminal) and a second current inlet/outlet terminal (second terminal) respectively provided at an end and the other end of the first fuse link, and a third current inlet/outlet terminal (second terminal) and a fourth current inlet/outlet terminal (third terminal) provided at an end and the other end of the second fuse link.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: August 25, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Hiroaki Ohkubo, Yasutaka Nakashiba
  • Patent number: 7580293
    Abstract: A programmable non-volatile semiconductor memory device includes a select gate 3, arranged in a first region on a substrate, a floating gate 6 arranged in a second region neighboring to the first region, a first diffusion region 7 provided in a third region neighboring to the second region, a control gate 11 arranged on the floating gate 6, and a driving circuit 22 adapted for controlling voltages applied to the substrate 1 (well 1a), select gate 3, first diffusion region 7 and control gate 11. The driving circuit performs control so that, during erasure operation, voltages applied to select gate 3 and the control gate 11 are negative, with the remaining voltage, applied to the substrate 1 (or well 1a), being positive. The device permits erasure operation at a lower voltage.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: August 25, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Kohji Kanamori, Kenichi Kuboyama
  • Patent number: 7579266
    Abstract: When the film thickness of an insulating film on a fuse connected to a circuit is not uniform within a wafer surface, there was a problem that disconnection of the fuse might become insufficient due to the insufficient intensity of a laser or disconnection of even an adjacent fuse due to excessive laser irradiation might occur. Further, a problem also occurred that after disconnection of the fuse, moisture entered from exterior through the region in which the fuse has been disconnected, so that the quality of a film underlying the fuse was adversely affected. After a SiON film, a SiN film, and a SiO2 film have been formed to cover the fuse in this stated order, etching is performed to the SiN film, which is an etching stopper film. The SiON film having a uniform and desired film thickness is thereby formed on the fuse.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: August 25, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Takashi Sakoh
  • Publication number: 20090206410
    Abstract: Semiconductor devices required forming a stress control film to handle different stresses on each side when optimizing the stress on the respective P channel and N channel sections. A unique feature of the semiconductor device of this invention is that P and N channel stress are respectively optimized by making use of a stress control film jointly for the P and N channels that conveys stress in different directions by utilizing the film thickness.
    Type: Application
    Filed: January 21, 2009
    Publication date: August 20, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Hitoshi Mitani
  • Publication number: 20090206475
    Abstract: A method of manufacturing a semiconductor device which includes step of forming a lower resist film over an insulating interlayer; forming a first opening having a circular geometry in a plan view, and second to fifth openings arranged respectively on four sides of the first opening, in the lower resist film; and etching the film-to-be-etched while using the lower resist film as a mask, wherein in the step of etching the film-to-be-etched, a hardened layer is formed in a region of the lower resist film fallen between the first opening and each of the second to fifth openings, and the film-to-be-etched is etched while using the hardened layers as a mask, so as to form a contact hole having a rectangular geometry in a plan view in the film-to-be-etched at a position correspondent to the first opening of the lower resist film.
    Type: Application
    Filed: January 16, 2009
    Publication date: August 20, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Kouichi KONISHI
  • Publication number: 20090207192
    Abstract: A neutralization switch is provided for each of the RGB (red, green and blue) colors to control the charge neutralization periods of those RGB colors respectively. Each of the neutralization switches has an on-resistance value that differs among the RBG colors. A low value is set for the on-resistance value of the neutralization switch of the data line corresponding to green of which visual sensitivity is high so as to shorten the charge neutralization period, thereby extending the driving periods in which the subsequent gradation signals are to be output respectively.
    Type: Application
    Filed: February 4, 2009
    Publication date: August 20, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Yoshiharu Hashimoto
  • Publication number: 20090206664
    Abstract: Provided is a power supply circuit generating a desired voltage by voltage multiplication, and satisfying both a demand to reduce current consumption and a demand to enable operation with a low power voltage at the same time. A power supply circuit of the present invention includes: a voltage generating circuit for generating internal voltages VI1 and VI2 from a power supply voltage VDD; a voltage step-up/down circuit for generating voltages VO1 to VO3 each having a different level by multiplying the internal voltages VI1 and VI12; and a voltage comparison circuit for comparing the voltage VO2 with the power supply voltage VDD. The voltage generating circuit is configured to select one of the internal voltages VI1 and VI2 according to an output of the voltage comparison circuit. Additionally, a voltage multiplication rate of the voltage multiplication circuit is switched according to the output of the voltage comparison circuit.
    Type: Application
    Filed: February 13, 2009
    Publication date: August 20, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Makoto Sasaki, Kentaro Tanaka, Takafumi Natsume
  • Publication number: 20090207581
    Abstract: A longest wiring and a shortest wiring alongside each other among the plurality of wirings are placed. Then, a longest wiring from among remaining wires which have not being placed yet, alongside an outside of a space surrounded by the wirings already placed and on a side of a shorter wiring of the wrings placed at outermost ends are placed. A shortest wiring from among remaining wires which have not placed yet, alongside an outside of a space surrounded by the wirings already placed and on a side of a longer wiring of the wirings placed at outermost ends is placed. These two processes are repeated.
    Type: Application
    Filed: February 4, 2009
    Publication date: August 20, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Tamotsu Watarai
  • Patent number: 7576964
    Abstract: An overvoltage protection circuit is for a circuit of an output MOS transistor and a load connected in series between a first power supply and a second power supply. The overvoltage protection circuit contains a control signal circuit, a dynamic clamping circuit, a control switch, and a serge detecting circuit. The control signal circuit is connected between a gate of said output MOS transistor and said load, and the dynamic clamping circuit is connected with said gate of said output MOS transistor. The control switch is connected between said first power supply and said dynamic clamping circuit and the serge detecting circuit which monitors a voltage of said first power supply and turns on said control switch when the voltage of said first power supply increases to a voltage higher than a predetermined voltage.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: August 18, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Akihiro Nakahara
  • Patent number: 7576524
    Abstract: In a constant voltage generating apparatus where an output circuit is controlled in accordance with a control voltage, a voltage detection signal generating circuit generates a voltage detection signal in accordance with a difference between an output voltage signal of the output circuit and a first reference signal. A current detection signal generating circuit generates a current detection signal in accordance with a difference between an output current signal of the output circuit and a second reference signal. A control current generating circuit generates a control current in accordance with the voltage detection signal and the current detection signal. A control current-to-control voltage converting circuit converts the control current into the control voltage.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: August 18, 2009
    Assignee: NEC Electronics Corporatioon
    Inventor: Tsukasa Ohoka
  • Patent number: 7576405
    Abstract: A semiconductor device is composed of: a power control region within which function cells are arranged; a basic power supply line overlapping said power control region, and positioned in a power supply interconnection layer; a virtual power supply line arranged in said power control region in a direction perpendicular to said basic power supply line, said function cells being connected to said virtual power supply line; a ground line arranged in said power control region in said direction perpendicular to said basic power supply line; a switch cell including a metal interconnection positioned in a metal interconnection layer different from said power supply interconnection layer, and a switch element electrically connected between said metal interconnection and said virtual power supply line; and a via contact connected between said basic power supply line and said metal interconnection. The switch cell is positioned within power control region.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: August 18, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Tetsuya Katoh
  • Patent number: 7576674
    Abstract: Disclosed is a data driver including a reference voltage generation circuit that generates and outputs a plurality of reference voltages, a decoder circuit that selects from among the reference voltages n (where n is an integer greater than or equal to two) reference voltages inclusive of reference voltages that may be identical and outputs the n reference voltages from n output terminals thereof, and an amplifying circuit that includes n differential circuits, a feedback resistor, and a resistor. The n output terminals are connected to non-inverting input terminals of the n differential circuits, respectively. The amplifying circuit outputs an output voltage obtained by operating and synthesizing the n reference voltages. One end of the feedback resistor is connected to an output terminal of the amplifying circuit, and the other end is connected to inverting input terminals of the n differential circuits connected in common.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: August 18, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Hiroshi Tsuchi
  • Publication number: 20090201758
    Abstract: An integrated circuit design method is provided in which memory instances are assigned to memory macros integrated within an integrated circuit. The integrated circuit design method includes: assigning a plurality of memory instances operating at the same operation frequency to a single memory macro; arranging a frequency multiplier which receives a first clock signal to generate a second clock signal through frequency multiplication of the first clock signal, and feeds the second clock signal to the plurality of memory instances; and arranging a control circuit which selects the memory instances in synchronization with the first clock signal.
    Type: Application
    Filed: February 11, 2009
    Publication date: August 13, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Masaharu Mizuno, Masahiro Suzuki, Shinichi Uchino
  • Publication number: 20090201237
    Abstract: An operational amplifier circuit includes: an input differential stage circuit supplied with power supply voltages in a first voltage range; and an output stage circuit supplied with power supply voltages in a second voltage range which is different from the first voltage range. The operational amplifier circuit amplifies a signal supplied to the input differential stage circuit and outputs the amplified signal from the output stage circuit to drive a load.
    Type: Application
    Filed: February 9, 2009
    Publication date: August 13, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Kouichi Nishimura
  • Publication number: 20090201656
    Abstract: A semiconductor package is obtained by separately preparing a board having, as formed on the surface thereof, an interconnect pattern containing a fine pattern having a narrow interconnect pitch adapted to connection with a high-pin-count device, and a board having, as formed on the surface thereof, an interconnect pattern containing no fine pattern but only a rough pattern having a wide interconnect pitch adapted to connection with a low-pin-count device; by mounting the devices respectively on these boards; and by stacking these boards.
    Type: Application
    Filed: January 15, 2009
    Publication date: August 13, 2009
    Applicant: NEC Electronics Corporation
    Inventor: Hiroki Shibuya