Abstract: A design method according to an aspect of the present invention includes laying out a plurality of functional blocks of a design circuit based on a first netlist, creating a second netlist by adding a first path information to the first netlist, the first path information corresponding to an inter-block line connecting between the functional blocks, creating a third netlist by adding a second path information to the second netlist, the second path information corresponding to an intra-block line connected to a terminal of each functional block from inside of each functional block, creating a fourth netlist that models a line resistance and a line capacitance of an inter-instance line which combines the first path information and the second path information included in the third netlist, and estimating a delay time from information based on the fourth netlist.

Abstract: A communication device communicates by reserving a Medium Access Slot (MAS) based on WiMedia_Alliance. The communication device includes a control part that generates negotiation request information, the negotiation request information requesting a reservation change so that an own device uses a MAS having been reserved by other communication device, and a host controller that sends the negotiation request information to the other communication device and receives a response accommodating the reservation change from the other communication device. After receiving the response, the control part sets a MAS reserved by the other communication device to as a MAS used by the own device.

Abstract: A DC (direct current) converter includes a PWM (pulse width modulation) pulse generation unit outputting a PWM pulse signal whose duty ratio is controlled in accordance with an output voltage, a PFM (pulse frequency modulation) pulse generation unit outputting a PFM pulse signal whose pulse output interval is controlled in accordance with an output voltage, a selection circuit selecting and outputting any one of the PWM pulse signal and the PFM pulse signal in response to a selection signal, a drive circuit unit driving a load and generating an output voltage on the basis of a signal outputted from the selection circuit, and a switching control unit outputting the selection signal. When the selection signal is in a second state, the switching control unit detects a fact that the number of pulses of the PFM pulse signal in a measurement period increases to or above a set value of the maximum number of pulses, and switches the selection signal to a first state.

Abstract: Provided is a communication network system capable of effectively utilizing a telephone number and a terminal identity assigned to a communication terminal. The communication terminal transmits to a network server a communication start request including a temporary telephone number and a mobile station identity which are previously permitted to use. The network server verifies the communication terminal based on the mobile station identity. At this point, the network server informs the communication terminal of the telephone number necessary for the communication terminal to continue communication. The communication terminal originates a call by using the telephone number and the mobile station identity.

Abstract: A semiconductor according to an embodiment of the invention has a supply voltage generator circuit generating a supply voltage based on a received radio signal, a voltage detector circuit detecting a reference voltage dependent on the supply voltage, a memory circuit storing data, and a control circuit executing write operation to the memory circuit according to a reference voltage detected by the voltage detector circuit.

Abstract: A coupling oxide film is formed on a silicon substrate, a polysilicon film is further formed thereupon, and a low-temperature oxide film is deposited to a thickness of 10 nm, for example. Next, a silicon nitride film is formed on this low-temperature oxide film, and selectively removed by dry etching. At this time, the low-temperature oxide film serves as an etching stopper film, so the low-temperature oxide film and polysilicon film are not over-etched. Subsequently, the polysilicon film is dry-etched, forming a recess. A floating gate is then formed of the polysilicon film.

Abstract: A delay locked loop (DLL) circuit includes a first DLL section configured to receive a reference clock signal, to delay the reference clock signal in response to a first control signal, and to output a phase delayed signal having a predetermined phase delay. A second DLL section delays the reference clock signal in response to a second control signal, and generates the second control signal based on the reference clock signal delayed in the second DLL section and the phase delayed signal. An input signal delay section delays an input signal in response to the second control signal.

Abstract: A semiconductor device includes an interlayer insulating film formed on or over a semiconductor substrate. An opening is formed in the interlayer insulating film and reaches a lower layer metal wiring conductor. A metal plug is formed by filling the opening with Cu containing metal via a barrier metal. The interlayer insulating film includes the insulating film which includes a carbon containing silicon oxide (SiOCH) film which has Si—CH2 bond in the carbon containing silicon oxide film. The proportion of Si—CH2 bond (1360 cm-1) to Si—CH3 bond (1270 cm-1) in the insulating film is in a range from 0.03 to 0.05 measured as a peak height ratio of FTIR spectrum.

Abstract: A decoding device according to the one embodiment of the invention includes: a first decoder performing a first decoding based on first encoded data obtained by encoding unencoded data, and second soft-output data to generate first soft-output data; a second decoder performing a second decoding based on second encoded data obtained by interleaving the unencoded data and encoding the interleaved data, and the first soft-output data to generate the second soft-output data; and a hard decision part outputting decoded data through hard decision on the first soft-output data.

Abstract: A semiconductor device that improves adhesion between a resin and a die pad and prevents cracking of the resin includes: a semiconductor chip; a die pad on which the semiconductor chip is mounted; a bonding agent for bonding the semiconductor chip to the die pad; a plurality of inner leads provided at the outer periphery of the die pad; outer leads extending from the inner leads; bonding wires connecting the inner leads to the semiconductor chip mounted on the die pad; and a resin for sealing the inner leads, the die pad, the semiconductor chip, the bonding agent and the bonding wires. The bonding agent is further disposed in all or part of a margin of the die pad at a peripheral portion where the semiconductor chip is mounted, and a plurality of dimples are formed in the surface of the bonding agent in the die pad margin.

Abstract: Disclosed is an impedance adjustment circuit including a comparator and a resistor control circuit. The comparator compares the resistance value of an external resistor and that of a replica resistor that forms a replica of a terminal resistor. The resistor control circuit includes a replica resistor control counter, a resistor-under-adjustment control signal holding circuit and a monitor circuit. The replica resistor control counter counts up and down based on the comparison result by the comparator to output a control signal to the replica resistor. The resistor-under-adjustment control signal holding circuit holds a control signal that is delivered to the terminal resistor.

Abstract: A layout design method of a semiconductor integrated circuit includes degenerating a layout netlist extracted from layout data, comparing the layout netlist after the reduction with a circuit diagram netlist, and creating a layout circuit association table of a layout cell after the reduction and a circuit element. The method includes creating a before and after reduction association table based on the layout netlist before and after the reduction, counting the number of layout elements in a layout cell area before the reduction, comparing the counted number of layout elements and the number of degenerated elements, and creating mapping information associating the layout cell with the circuit element.

Abstract: A method for testing a semiconductor device having plural transmitting (TX) circuits and plural receiving (RX) circuits at a low cost and in a short time. The semiconductor device includes two or more pairs of transmitting and receiving circuits. Each of the transmitting circuits converts parallel data to serial data and transmits the converted serial data to external while each of the receiving circuits receives serial data from external and converts the received serial data to parallel data. Furthermore, the semiconductor device includes a device that enables two or more selected pairs of transmitting and receiving circuits to be connected serially and alternately. The semiconductor device can be configured so that the serially connected transmitting or receiving circuit in the first stage inputs a test signal to be compared with a signal output from the serially connected receiving or transmitting circuit in the last stage.

Abstract: A semiconductor device manufacturing method, a semiconductor device manufacturing equipment and a computer readable medium storing a computer program provide for easily identifying a cause of a deviation of pattern dimensions from the objective dimension. A first storage section stores a relation between a PEB temperature and a photoresist dimension of a post-lithography. A second storage section stores a relation between a PEB temperature and a post-etching dimension. A primary correction section determines a first corrected PEB temperature for conforming the photoresist dimension of a post-lithography to the objective dimension, using the relation data stored in the first storage section. A secondary correction section determines the second corrected PEB temperature for conforming the post-etching dimension using the first corrected PEB temperature to the objective dimension, using the relation data stored in the second storage section.

Abstract: An integrated circuit design method includes: classifying flipflops arranged around a macro based on a netlist of a integrated circuit incorporating the flipflops and the macro; and generating a flipflop-replaced netlist from the netlist. In classifying the flipflops, a flipflop which is connected to an input terminal of the macro directly or through an input-side logic cone and operated on the same clock signal as the macro is classified as a control type, and a flipflop which has a data output connected to an input terminal of the macro directly or through the input-side logic cone and operated on a different clock signal is classified as a hold type.

Abstract: An object of the present invention is to solve the problem that the number of pads increases due to high packaging density and the size of semiconductor devices increases due to increase of the pad density. A semiconductor device according to the present invention uses a conductor trace on an interconnection substrate to interconnect two nonadjacent pads.

Abstract: In order to provide a wiring board having a structure different from a conventional structure and a manufacturing method therefor, a wiring board (1) includes: a first principal surface (6a); a second principal surface (6b) being opposed to the first principal surface (6a); a plurality of wiring layers (81, 82, 83, and 84); and a through hole (30) piercing at least one set of neighboring wiring layers among the plurality of wiring layers in a lamination direction of the at least one set of neighboring wiring layers. The through hole (30) includes a flat surface (21) that has conductivity and is decoupled electrically into at least two blocks formed on its surface at least partially.

Abstract: A design support system which supports designing a semiconductor device is provided. The design support system includes a gate film information acquisition section and a maximum allowable antenna ratio setting section. The gate film information acquisition section acquires information on the thickness of the gate insulating film of a semiconductor device which has been designed. The gate insulating film thickness refers to a physical film thickness. The maximum allowable antenna ratio setting section sets maximum allowable antenna ratios for a gate electrode according to the film thickness information acquired by the gate film information acquisition section. Hence, a designer designing a semiconductor device can set concrete values when changing maximum allowable antenna ratios according to the thickness of the gate insulating film.

Abstract: A semiconductor memory circuit includes first and second bit lines making a first pair, third and fourth bit lines making a second pair, a memory cell having a first inverter coupled between the first pair, a second inverter coupled between the second pair, a third inverter coupled between first and third bit lines and a fourth inverter coupled between second and fourth bit lines. The memory cell further includes a first access switch inserted between first bit line and the first inverter, second access switch inserted between second bit line and the second inverter, third access switch inserted between third bit line and the third inverter and fourth access switch inserted between fourth bit line and the fourth inverter.

Abstract: A power-source potential control circuit has: an output terminal outputting a control signal to a power-source generating device which generates a power-source potential in accordance with the control signal; an input terminal connected to an output of the power-source generating device; and a control unit configured to make a comparison between a trimming potential depending on a first potential at the input terminal and a predetermined reference potential and to output the control signal corresponding to a result of the comparison. In a trimming operation mode, the control unit changes the trimming potential in accordance with the result of the comparison.