Abstract: A pulse signal generator includes a period setting unit that receives a period set signal including an information indicative of a pulse period, and that outputs a period control signal controlling the pulse period, a duty ratio setting unit that receives a duty ratio set signal including an information indicative of a duty ratio of a pulse, that receives a signal including the pulse period set in the period setting unit, and that generates a duty ratio control signal controlling the duty ratio of the pulse on a basis of the pulse period and the duty ratio set signal, and a pulse generation unit that generates a pulse signal including the pulse period and the duty ratio of the pulse on a basis of the period control signal and the duty ratio control signal.

Abstract: A test circuit according to the present invention includes: a synthesis circuit that synthesizes a first test result signal output from a first test target circuit in response to a test instruction, and a second test result signal output from a second test target circuit in response to the test instruction; an inter-block delay generation circuit that delays the second test result signal with respect to the first test result signal; and a test result holding circuit that holds a synthesized test result signal every predetermined timing, the synthesized test result signal being output from the synthesis circuit

Abstract: An external-electrode discharge lamp has a light-permeable, electrically insulative outer casing having a closed hollow space defined therein. A discharge medium is sealed in the outer casing. An external electrode is disposed on an outer surface of the outer casing for causing a dielectric barrier discharge in the discharge medium. The external electrode comprises a plate of an electrically conductive material and is brazed to the outer surface of the outer casing by a brazing material disposed fully circumferentially on the outer surface of the outer casing.

Abstract: A semiconductor device has: an insulating substrate; a first semiconductor layer of a first conductivity type formed on the insulating substrate; a first vertical field effect transistor of the first conductivity type, one of whose source and drain being formed on the first semiconductor layer; a second semiconductor layer of a second conductivity type formed on the insulating substrate; and a second vertical field effect transistor of the second conductivity type, one of whose source and drain being formed on the second semiconductor layer. The first semiconductor layer and the second semiconductor layer are directly in contact with each other.

Abstract: A system and method for dynamically allocating sub-carriers between the nodes of an optical OFDMA ring network or an OFDMA passive optical network. A carrier allocation system assigns sub-carriers according to a utility function based on real-time measurements of arrival data rates and queue length variance.

Abstract: A distributed shared memory multiprocessor that includes a first processing element, a first memory which is a local memory of the first processing element, a second processing element connected to the first processing element via a bus, a second memory which is a local memory of the second processing element, a virtual shared memory region, where physical addresses of the first memory and the second memory are associated for one logical address in a logical address space of a shared memory having the first memory and the second memory, and an arbiter which suspends an access of the first processing element, if there is a write access request from the first processing element to the virtual shared memory region, according to a state of a write access request from the second processing element to the virtual shared memory region.

Abstract: A memory controller has a control unit receiving a transfer data from a transmission circuit and executing a burst transfer of the transfer data to a reception circuit. The transmission circuit transmits a first data of a first bit length for a first burst times by a burst transmission. The amount of the transfer data is equal to a product of the first bit length and the first burst times. The reception circuit receives a second data of a second bit length for a second burst times by a burst reception. When the amount of the first data received by the control unit becomes equal to or more than a product of the second bit length and the second burst times, the control unit transfers the received first data as the second data to the reception circuit, regardless of the number of the first data received by the control unit.

Abstract: There is disclosed a method for switching access folders in accordance with a confidential mode. In this method, a confidential root directory is located below a normal root directory. A directory structure constituted by the at least one confidential folder other than a confidential root directory is the same as that constituted by at least one normal folder other than a normal root directory. A file access request from an application program to a disk device is received. If the application program is operating as a process in a confidential mode, file access to the confidential file in the confidential folder is executed through a kernel, by rewriting a specified file path name with a file path name corresponding to the confidential folder below the confidential root directory. If the application program is operating as a process in the normal mode, file access to the confidential file in the confidential folder is not permitted.

Abstract: In an evaporator for evaporating mists of liquid raw material to thereby generate start gas for layer-formation, an evaporator body has an evaporator chamber defined therein, and a mist supply throat for introducing the mists into the evaporating chamber. The evaporator chamber is defined by a principal evaporating face which opposes to the mist supply throat. The evaporator body also has a start-gas supply passage which is formed therein between the mist supply throat and the principal evaporating face such that the start gas flows out of the evaporating chamber through the start-gas supply passage. A ridge member is provided on an inner side wall surface of the evaporating chamber between the start-gas is supply passage and the principal evaporating face so that a tip edge of the ridge member is directed to the principal evaporating face.

Abstract: An optical transmitter with an external modulator includes a light-emitting unit emitting a continuous wave light, a modulation unit modulating the continuous wave light in accordance with an electric signal, a first terminal applying a first positive voltage to a cathode of the light-emitting unit and a cathode of the modulation unit, a second terminal applying a second positive voltage of a constant value to an anode of the light-emitting unit, and a third terminal applying a third positive voltage with the electric signal to an anode of the modulation unit. The second positive voltage is set to a value higher than the first positive voltage, and the third positive voltage is set to a value lower than the first positive voltage.

Abstract: A logic circuit is provided with a first differential transistor pair (Q1, Q2) operable in response to a data signal input thereto; a current source for supplying a current to the first differential transistor pair (Q1, Q2); a first transistor (Q5) connected between a common emitter of the first differential transistor pair (Q1, Q2) and the current source, and operable in response to a clock signal input thereto; and a first potential stabilizing circuit (30a) connected to a first junction between the common emitter of the first differential transistor pair (Q1, Q2) and a collector of the first transistor (Q5), for stabilizing a potential at said first junction.

Abstract: A level shifter in which short circuit current and the increase in delay are reduced when a first power source is controlled. In a level shifter for converting a signal level of a first logic circuit to which a first power source is supplied into a signal level of a second logic circuit to which a second power source is supplied, the circuit includes a switching circuit between a GND power source terminal of a level shift core circuit and a GND power source. The switching circuit is controlled by a third logic circuit which generates a control signal under control of the first power source, and a pull-up/pull-down circuit at an output of the level shift core circuit. The pull-up and/or pull-down circuit is controlled by the third logic circuit.

Abstract: A hardware is used to perform an SSDT processing, thereby avoiding performance degradation than otherwise would occur due to load increase caused by a software processing, and thereby realizing a base station that can instantaneously perform a transmission control and provide a high speed site selection. In order to perform a site selection diversity power control (SSDT) for the purpose of reducing the amount of interference that would be caused by transmitting the same data to a plurality of cells or antennas during soft-handover, an encode processing part (1) is used to add a transmission control bit to the transmitted data. In response to this transmission control bit, a transmission control signal selecting circuit (206) selects a transmission control signal of destination.

Abstract: On adjusting a target specification data error predicted value so as to become larger on detecting maneuver of a target, the target specification data error predicted value is adjusted, in consideration of type of the maneuver and a course of the target, so as to make a direction of varying specification data large and to make a direction of constant specification data small. It is therefore possible to quickly recover a delay of the following of the varying specification data and to avoid increasing an error of the constant specification data.

Abstract: Optical waveguide device has waveguide strip-shaped in the depth direction of the drawing and protruding from peripheral portion. A core (not illustrated) is disposed inside waveguide. Wall to be cut is integrated with waveguide to form one core layer. No unevenness occurs in a cutting line of wall indicated with broken line. Accordingly, high-precision cutting is enabled by cutting wall along the cutting line.

Abstract: The present invention provides, as a method of analyzing the C-terminal amino acid sequence of a peptide with use of reaction technique for successively releasing the C-terminal amino acids, in which undesirable side reactions, such as cleavage of a peptide bond at the middle of the peptide, can be prevented and chemical treatments therein can be carried out under widely applicable conditions in the course of successive release of the C-terminal amino acids from a peptide, such a method comprising steps of dehydrating the gel on which a target peptide that has been separated by gel electrophoresis is held in the bound state; immersing it in a mixture solution of an alkanoic acid anhydride added with a small amount of a perfluoroalkanoic acid in a dipolar aprotic solvent to re-swell the gel carrier, forming a 5-oxazolone structure, at a temperature chosen in the range of from 30° C. to 80° C.

Abstract: In a node having first, second, and third layers, a packet (or a cell) is mapped in the first layer. The first layer judges whether the packet (or the cell) is to be dropped at the node or to be hopped to a next node. The first layer transmits the packet to the third layer through the second layer when the first layer judges that the packet is to be dropped at the node. The first layer transmits, when the first layer judges that the packet is to be hopped to the next node, the packet to the next node by making the packet cut through the first layer.

Abstract: A semiconductor storage device in which product cost is reduced includes a memory cell section (cells belonging to word lines) and a bypass section (cells belonging to bypass word lines). The memory cell section has a select gate, floating gates, a first diffusion region, a second diffusion region and a first control gate. The bypass section has the first select gate, the first diffusion region, the second diffusion region and a second control gate. The second control gate controls a channel in an area between the select gate and the first diffusion region or between the select gate and the second diffusion region. The channel of the bypass section becomes a current supply path when a cell of the memory cell section is read out.

Abstract: The present invention provides a relief method of competition between a Down Link RRC message and inter-cell movement of user equipment which can continue communication even when acknowledgment of the Down Link RRC message cannot be performed. An RLC layer of the radio network controller (RNC) divides a Down Link RRC message into RLC AMD_PDU and transmits them, and gives an RLC error notice to an RRC layer from the RLC layer when a number of RLC AMD_PDU resending is exceeded because RLC ACK cannot be received from user equipment (UE). An RRC layer of the radio network controller activates a timer. When receiving CELL UPDATE within a fixed period, the RRC layer regards the RLC error as competition with inter-cell movement of the user equipment to reset the RLC layer of the radio network controller. The RRC layer of the radio network controller makes RLC RESET INDICATOR be TRUE in RRC:CELL UPDATE CONFIRM from the radio network controller so as to reset the RLC layer of the user equipment.

Abstract: Disclosed is a clock-and-data recover circuit in which a data sampling circuit, a phase comparator, a phase controller and a phase interpolator make up a loop. The data sampling circuit samples serial input data, and the phase comparator receives an output from the data sampling circuit to detect the phase relationship between clock and the data. The phase controller outputs a phase control signal based on the result of phase comparison of the phase comparator to output a phase control signal. The phase interpolator receives a multi-phase clock composed of plural clock signals with different phases and supplies a clock signal having the phase interpolated based on the phase control signal, to the data sampling circuit. The clock and data recovery circuit further includes a second phase interpolator and a second data sampling circuit. The phase controller generates and outputs a second phase control signal to the second phase interpolator.