Abstract: A charge pump type booster circuit generates a positive or negative boosted output voltage by switching booster paths one by one. This charge pump type booster circuit includes a plurality of booster paths, each of the plurality of booster paths including at least one booster capacitor, wherein a number of the booster capacitor at each of the plurality of booster paths is different between one booster path and the other booster path. This makes it possible to suppress an increase in a number of an external capacitor for setting an output voltage of the booster circuit constant.

Abstract: The semiconductor device 1 has a semiconductor chip 10 (first semiconductor chip) and a semiconductor chip 20 (second semiconductor chip). The semiconductor chip 20 is formed on the semiconductor chip 10. The semiconductor chip 20 is constituted by comprising a semiconductor substrate 22. The semiconductor substrate 22, which is an SOI substrate, is constituted by comprising an insulating layer 34, and a silicon layer 36, which is provided on the insulating layer 34, including a circuit forming region A1. The insulating layer 34 functions as a protective film (a first protective film) covering a lower face (a face opposite to the semiconductor chip 10) of the circuit forming region A1. A protective film 38 (a second protective film) is provided on the semiconductor substrate 22. The protective film 38 covers a side face of the circuit forming region A1.

Abstract: In a node having first, second, and third layers, a packet (or a cell) is mapped in the first layer. The first layer judges whether the packet (or the cell) is to be dropped at the node or to be hopped to a next node. The first layer transmits the packet to the third layer through the second layer when the first layer judges that the packet is to be dropped at the node. The first layer transmits, when the first layer judges that the packet is to be hopped to the next node, the packet to the next node by making the packet cut through the first layer.

Abstract: An active matrix addressing LCD device having an active matrix substrate on which conductive lines are formed is provided, which suppress the AI hillock without complicating the structure of the lines and which decreases the electrical connection resistance increase at the terminals of the lines, thereby improving the connection reliability. The device comprises an active matrix substrate having a transparent, dielectric plate, thin-film transistors (TFTs) arranged on the plate, and pixel electrodes arranged on the plate. Gate electrodes of the TFTs and scan lines have a first multilevel conductive structure. Common electrodes and common lines may have the first multilevel conductive structure. Source and drain electrodes of the TFTs and signal lines may have a second multilevel conductive structures. Each of the first and second multilevel conductive structures includes a three-level TiN/Ti/Al or TiN/Al/Ti structure or a four-level TiN/Ti/AI/Ti structure.

Abstract: A mobile telecommunication terminal device is provided which is capable of preventing an excessive increase in transmitting power to be fed from a base station even if a burst error occurs in a mobile unit. The mobile telecommunication terminal device has an error frequency calculating section to calculate a frequency of detection of errors in received data, a target transmitting power setting section to decrease a set value of a target SIR (Signal to Interference Power Ratio) when the frequency of detection of errors is not larger than the target SIR, while the frequency of detection of errors exceeds the target detection frequency value, to increase the set value of the target SIR, an SIR measuring section, an SIR comparing section, a transmitting power requesting section, and an error frequency correcting section.

Abstract: A semiconductor device includes a capacitor with an MIM structure, by which the dimensional accuracy of the device is improved, and a stable capacitance value is given. The semiconductor device 100 includes: a semiconductor substrate 102; a capacitor forming region 130 in which an MIM capacitor is formed, which has an insulating interlayer 104 formed on the semiconductor substrate 102, a first electrode 110, and a second electrode 112, and the first electrode 110 and the second electrode 112 are arranged facing each other through the insulating interlayer 104; and a shielding region 132 which includes a plurality of shielding electrodes 114 formed in the outer edge of the capacitor forming region 130 and, at the same time, set at a predetermined potential in the same layer as that of the MIM capacitor on the semiconductor substrate 102, and shields the capacitor forming region 130 from other regions.

Abstract: There is provided a semiconductor apparatus which includes a substrate, a semiconductor chip mounted above the substrate, a first resin filled between the substrate and the semiconductor chip, and a second resin formed on the substrate and extending from a side surface of the semiconductor chip toward an outer edge of the substrate. The second resin extends from an intersection of an extension of the side surface of the semiconductor chip and the substrate toward the outer edge of the substrate so that a first stress generated on a contact surface between the first resin and the semiconductor chip and a second stress generated on a contact surface between the first resin or the second resin and the substrate balance out each other.

Abstract: When receiving a write message associated with data, an input/output controller issues a write-request message to a home processor node which holds the data in a memory. When receiving the write-request message, a memory controller in the processor node executes a consistency process on the basis of information, regarding the state of the data, stored in a directory, and sends a write-permission message to the input/output controller which has issued the write-request message. In response to the received write-permission message, the input/output controller in an input/output node issues an update message, serving as a write message, to the home processor node. In response to the received update message, the memory controller in the process node updates the data in the main memory. In the above process, when receiving a plurality of write messages from input/output devices, the input/output controller issues write-request messages irrespective of the progress of a preceding write message.

Abstract: A processor performs layout analysis, and classifies pieces of bitmap data into a character area and a picture area. The processor divides each of the character area and the picture area into a plurality of tiles having a predetermined shape, thereby creating a table including information representing either character attribute or picture attribute in association with each tile number. The processor performs scalar quantization for data of each tile using a quantization coefficient for characters or pictures, based on the created table. The processor encodes the data of each tile using an SNR progressive technique or a resolution progressive technique, and performs post quantization for the data using a quantization parameter for characters or pictures. Then, the processor stores the encoded data into a storage device.

Abstract: A device for processing data read from a memory, the data including a word and a parity element with respect to the word, the device including a data recovery circuit that corrects error data in the word using a correction code generated from the parity element.

Abstract: A cell core unit and its peripheral circuit are driven by a relatively low voltage power supply. A constant voltage that does not depend on the power supply voltage is provided as a boosted voltage (VBOOST) to be supplied to a control signal for a word line of the cell core unit. A sense amplifier amplifies a higher voltage level of a bit line to the power supply voltage. Then, a circuit for generating a signal for defining the transition timing and/or the pulse width of a control signal from the peripheral circuit to the cell core unit performs signal delay using a delay circuit having a characteristic in which a delay time thereof decreases with reduction of the provided power supply voltage.

Abstract: A multi-band wireless transceiver having a plurality of signal-processing paths, and further having a function of making wireless communication through a plurality of frequency bands by selecting one of the signal-processing paths, includes a band identification circuit for identifying a frequency band, the band identification circuit identifying a frequency band in dependence on a frequency-band information received from a controller which controls an operation of the multi-band wireless transceiver, and selecting one of the signal-processing paths in accordance with the identified frequency band.

Abstract: A figure reading apparatus capable of increasing the processing rate while maintaining the recognition precision, includes an image input apparatus for inputting a color image and a data processing apparatus for conducting processing on the input color image. The figure reading apparatus has a main color extraction function of extracting main colors contained in the color image and resolving the color image into main color images respectively of the main colors extracted from the input color image, a projection function of projecting points of extracted main colors on a three-dimensional space onto a plane by using a conversion expression, a candidate narrowing down function of removing combinations that need not be combined according to features of distance between main colors projected onto a two-dimensional space, and a combination generation function of combining images from candidates narrowed down and generating an image area candidate.

Abstract: A projector apparatus has a projection device for projecting an image onto a projection surface; at least two displacement sensors for detecting horizontal displacements of the projector apparatus, the displacement sensors being spaced a predetermined distance from each other; a rotational angle calculator for calculating a rotational angle of the projector apparatus in a horizontal plane using the predetermined distance and the horizontal displacements, the horizontal displacements being detected by the displacement sensors; and a distortion corrector for correcting distortion of the image by using the rotational angle, the image being projected by the projection device, wherein the rotational angle is calculated by the rotational angle calculator as a horizontal corrective angle.

Abstract: To provide a liquid crystal display backlight and a liquid crystal display device, which can improve the heat dissipating effect, can reduce the thickness and weight of the device. The liquid crystal display backlight includes: an emission light guide plate for emitting illuminating light for a liquid crystal display panel from one face; one and other mixed-color light guides mounted on a same plane of other face of the emission light guide plate via a spacer; a heat-dissipating spatial area provided between the mixed-color light guide plates; light-emitting devices disposed within the heat-dissipating spatial area; and reflectors for guiding output light, propagated inside each mixed-color light guide plate, towards corresponding end faces of the emission light guide plate from outside end face of each mixed-color light guide plate. A holding plate for holding the light-emitting devices is provided, facing each mixed-color light guide plate with an airing gap provided therebetween.

Abstract: Disclosed is a transmitter/receiver which performs transmitting and receiving operations based on CSMA/CA (Carrier Sense Multiple Access with Collision Avoidance) system. The transmitter/receiver includes a first unit, a second unit and a DC offset control unit. The first unit obtains a DC offset value generated in the transmitter/receiver and holds the obtained DC offset value. The second unit removes the held DC offset value from received data. The DC offset control unit causses the first unit to operate upon response to at least one of transmission completion and reception completion.

Abstract: A semiconductor memory device adapted to burst transmission is provided for improving flexibility of data write operation. The semiconductor memory device is composed of a memory array, a set of write registers, and an input buffer designed to sequentially receive a series of write data during a burst cycle, and to write the write data into the associated write registers. The device also includes a write release register containing a set of write release flags associated with the write registers, respectively, and a write release register controller asserting the associated write release flags in response to the write data being written into the associated write registers. The device also contains a write amplifier designed to concurrently write the write data contained in the write registers associated with the asserted write release flags, selectively, when the burst cycle is aborted in response to a control signal.

Abstract: The present invention provides a non-aqueous electrolyte secondary battery having excellent properties such as energy density and electromotive force and being excellent in cycle life, storage property and safety. In the present invention, the non-aqueous electrolyte secondary battery comprises a substance having a peak from 162.9 to 164.0 eV by XPS analysis on the anode surface.

Abstract: First pixels for the left eye and second pixels for the right eye in the semi-transmissive liquid crystal display panel are alternately disposed in the array direction of cylindrical lenses in a lenticular lens. A first transmissive region and a first reflective region are disposed in the first pixel for the left eye, and a second transmissive region and a second reflective region are disposed in the second pixel for the right eye. In this case, the first transmissive regions and the second reflective regions in the first pixels are alternately disposed and the second transmissive regions and reflective regions in the second pixels are alternately disposed in the longitudinal direction of the cylindrical lenses.

Abstract: A semiconductor device includes a first pad, a second pad and a third pad. The first pad and the third pad are electrically connected to each other. The first pad and the second pad are used for bonding. The second pad and the third pad are used for probing. According to this structure, Small size semiconductor device having high reliability even after a probing test can be provided.