Abstract: An image retrieval device and an image retrieval method are provided which are capable of improving performance of image retrieval, of retrieving images at higher speed with simplified configurations and of retrieving images by simplified calculating processes.

Abstract: In the mobile communication system, a total reception quality between a terminal and a base station is converged into a target quality, thereby suppressing a period in which the transmission power of a distant station becomes excessive.

Abstract: A tunable laser has a multiple ring resonator comprising a plurality of ring resonators having respective ring-shaped waveguides and respective different optical path lengths, an input/output side optical waveguide coupled to the multiple ring resonator, an optical input/output device such as a laser diode coupled to the input/output side optical waveguide, a reflection side optical waveguide coupled to the multiple ring resonator, an optical reflector coupled to the reflection side optical waveguide for removing light at an unwanted wavelength and reflecting light at a required wavelength, and a wavelength varying mechanism for changing the resonant wavelength of the multiple ring resonator.

Abstract: A wavelength tunable laser comprises a multiple ring resonator, an input/output side waveguide coupled to a ring resonator, a reflection side waveguide coupled to a ring resonator, a multiple ring resonator, a PLC substrate where the input/output side waveguide and the reflection side waveguide are formed, a high reflection film set on the reflection side waveguide, a SOA connected to the input/output side waveguide through a anti-reflection film, a film heater which is placed above a ring waveguide for wavelength tuning in the PLC substrate and provides heat to the ring waveguide for wavelength tuning, and a adiabatic groove, which restrain conducting heat provided by the film heater to the PLC substrate except the ring waveguide for wavelength tuning.

Abstract: In a protection circuit of an input/output terminal I/O, three types of PNP bipolar transistors are included. In a first PNP type bipolar transistor 10A, the emitter thereof is connected to the input/output terminal I/O, the base thereof is connected to a high-potential power supply terminal VDD, and the collector thereof is connected to a low-potential power supply terminal VSS. In a second PNP type bipolar transistor 10B, the emitter thereof is connected to the input/output terminal I/O, and the base and the collector thereof are connected to the high-potential power supply terminal VDD. In a third PNP type bipolar transistor 10C, the emitter thereof is connected to the low-potential power supply terminal VSS, and the base and the collector thereof are connected to the high-potential power supply terminal VDD.

Abstract: An electrical fuse comprises: an interconnect to be cut; and a first terminal and a second terminal which are respectively provided at both ends of the interconnect to be cut. The interconnect to be cut comprises: a first orientation film which contains copper as a main component and is oriented in a (111) plane; and a second orientation film which contains copper as a main component and is oriented in a (511) plane. The second orientation film is provided inside the first orientation film over a width direction of the first orientation film, which is perpendicular to a direction from the first terminal toward the second terminal, so as to partition the first orientation film. Accordingly, it becomes possible to securely cut the electrical fuse whose constituent material is copper, and moreover, to maintain a satisfactory cut state of the electrical fuse after the cutting.

Abstract: A semiconductor integrated circuit according to an exemplary embodiment of the present invention includes a plurality of memory cells connected to one word line; a plurality of sense amplifier circuits that are connected to the memory cells and divided into an N number of groups; and N number of data inversion processing circuits that respectively receive data read out from the N number of groups of sense amplifier circuits, in which after a sense amplifier circuit of a first group terminates operation, a sense amplifier circuit of a second group different from the first group operates, and each of the data inversion processing circuits performs data inversion processing based on the data read out from each of the groups of sense amplifier circuits, and outputs the data to an output terminal of each of the data inversion processing circuits.

Abstract: In a class AB amplifier circuit, an input stage circuit includes a first differential pair configured to receive a differential signal and a first current mirror circuit connected with the first differential pair through a first node. A middle stage circuit includes a floating constant current source connected with the first node, a first transistor whose gate is applied with a bias voltage, and a first constant current source connected with the first node through the first transistor. A last stage circuit includes a first output stage transistor whose gate is connected with the first node and which controls a voltage of an output terminal. A first phase compensation capacitance has one end connected with a first connection node between the first constant current source and the first transistor and the other end connected with the output terminal.

Abstract: In an exemplary aspect, the present invention provides a semiconductor memory device including sense amplifiers that drive bit lines to which memory cells are connected, and driver transistors that supply a power supply to the sense amplifiers, wherein the sense amplifiers are arranged in rows and constitutes a first sense-amplifier row in which transistors of a first conductive type are arranged and a second sense-amplifier row in which transistors of a second conductive type are arranged, and the driver transistors constitutes at least one transistor row including a first driver transistor of the first conductive type corresponding to the first sense-amplifier row and a second driver transistor of the second conductive type corresponding to the second sense-amplifier row between the first sense-amplifier row and the second sense-amplifier row.

Abstract: An operational amplifier circuit includes: an input stage for generating an internal current corresponding to a potential difference between inverting and non-inverting input terminals; and an output stage for driving an output terminal in response to the internal current. The output terminal includes: a floating current source through which the internal current flows; a PMOS transistor for driving the output terminal corresponding to a potential of a first terminal of the floating current source; and an NMOS transistor for driving the output terminal corresponding to a potential of a second terminal of the floating current source. The floating current source includes: a PMOS transistor whose source and drain are respectively connected to the first and second terminals; and an NMOS transistor whose drain and source are respectively connected to the first and second terminals. A depletion transistor is used as the latter NMOS transistor.

Abstract: An input stage of a differential amplifier includes a differential pair formed by an N-channel MOS transistor MN1 having a gate connected to an INM and an N-channel MOS transistor MN2 having a gate connected to an INP, both having sources connected to each other, a constant current source connected to the sources of the MN1 and MN2, and a variable current source connected to the sources of the MN1 and MN2. A subsequent-stage processing circuit having an intermediate stage and an output stage includes a phase compensation capacitor and outputs an output responsive to a change in the differential inputs by charging and discharging the phase compensation capacitor through the constant current source. The variable current source turns ON when the change reaches a level causing a parasitic capacitor at the sources of the differential pair to be discharged, and supplies a current for discharging the parasitic capacitor.

Abstract: A lead frame is provided that includes a base metal, a plated layer provided on a part of the surface of the base metal, and a thermal history monitor portion that discolors under heat load applied thereto, provided at another part of the base metal surface. A method of manufacturing a semiconductor device includes an assembly process including mounting a semiconductor chip on the lead frame, performing a wire bonding process thereby connecting the semiconductor chip and the lead frame, and encapsulating with a resin the wire-bonded semiconductor chip and the lead frame, and then performing an appearance check after the assembly process to inspect whether the thermal history monitor portion has discolored under heat load applied through the assembly process, thereby deciding whether an abnormality has emerged through the thermal history.

Abstract: A first printed circuit board for vertical polarized wave has a plurality of vertical polarized wave elements which serves as antenna elements, and a first feeder circuit which is connected to the plurality of vertical polarized wave elements. A second printed circuit board for horizontal polarized wave has a second feeder circuit which is connected to a plurality of horizontal polarized wave elements which serves as antenna elements, and is mounted with the plurality of horizontal polarized wave elements. A cutout portion is provided between the adjacent two vertical polarized wave elements of the first printed circuit board, and the first and second printed circuit boards are arranged parallel so that the horizontal polarized wave elements are arranged in the cutout portions of the first printed circuit board.

Abstract: A received electric field intensity estimates device estimates a received electric field intensity when a signal is received, by using at least a gain in a transmitting direction indicating the direction of the receiver viewed from a transmitter's side from among gains in the individual directions of the antenna's directive pattern of a transmitter's antenna, and outputs the estimated intensity. The device includes an averaging unit for averaging gains in the individual directions of the antenna's directive pattern within an angular range of an arrival wave angle indicating the direction of the signal arriving at the receiver, taken as the relevant direction; and a received electric field intensity calculation unit using at least the gain in the transmitting direction from among gains in the individual directions of the antenna's averaged directive pattern, and for outputting the result of the calculation as the estimated received electric field intensity.

Abstract: A method of fabricating a reactor composed of a coil, a core, and a container, capable of suppressing the core to break when a current flows in the coil to generate magnetic flux. In the method, the coil is formed by spirally winding a conductive wire. The coil is immersed in an insulating film in liquid with electrical insulation. The coil is placed in a furnace. Annealing for the coil and thermosetting for the insulating film are performed at a temperature within 250 to 320° C. for a period of time within 30 minutes to one hour before forming the core in the container. The coil is then disposed in the container. Inside and outside areas of the coil in the container is filled with a resin mixture composed of magnetic powder and resin. The resin mixture in the container is hardened to form the core.

Abstract: The present invention provides a conductive polymer suspension for providing a conductive polymer material having a high conductivity and a method for producing the same, and in particular, a solid electrolytic capacitor having a low ESR and a method for producing the same. The conductive polymer suspension can be is produced by: synthesizing a conductive polymer by chemical oxidative polymerization of a monomer giving the conductive polymer by using an oxidant in an aqueous solvent containing a dopant consisting of a low-molecular organic acid or a salt thereof, or a polyacid having a weight average molecular weight of less than 2,000 or a salt thereof.

Abstract: A main chip has a signal processing circuit for executing signal processing; a plurality of signal transmitting circuits for transmitting signals between the signal processing circuit and a signal transmitting circuit; and a control circuit for controlling operation/non-operation of the signal transmitting circuits in accordance with signal processing content of the signal processing circuit. Functional chips each have a signal processing circuit for executing auxiliary signal processing different from that of the signal processing circuit; and one or a plurality of signal transmitting circuits for transmitting signals between the signal processing circuit and the signal transmitting circuits. The main chip and the functional chips are stacked. The signal transmitting circuits and the signal transmitting circuit are non-contact-type signal transmitting circuits utilizing inductive coupling and are arranged so as to overlap when viewed from the stacking direction.

Abstract: An oscillation circuit according to an exemplary embodiment of the present invention includes: a power supply voltage terminal applied with a power supply voltage; a feedback loop circuit that outputs an oscillation frequency signal; and a correction circuit that corrects a time constant of the feedback loop circuit in accordance with the power supply voltage applied to the power supply voltage terminal. The configuration facilitates the correction of an oscillation frequency that varies depending on the fluctuation of the power supply voltage.

Abstract: An integrated circuit design method includes: obtaining layout data of an integrated circuit; and updating the layout data to modify the layout of the integrated circuit. In updating the layout data, a first via placed on an interconnection is replaced with a plurality of second vias having a size smaller than that of the first via. The positions of the via origin points of the second vias on the interconnection is different from the position of the via origin point of the first via on the interconnection.

Abstract: A gate line drive circuit includes: X level shift circuits configured to convert first address signals into second address signals; and a logic circuit configured to drive a selection gate line of N gate lines of a display unit based on the second address signals by supplying a first driving voltage to the selection gate line and by supplying a second driving voltage to non-selection gate lines of the N gate lines other than the selection gate line. X is an integer of 1 or more. N is equal to 2 raised to a power X. The first address signals includes X voltages each of which is a first voltage or a second voltage. The second address signals includes X driving voltages each of which is the first driving voltage or the second driving voltage.