Abstract: Systems and methods are disclosed for designing beamforming vectors for and allocating transmission rates to secondary users in a wireless cognitive network with secondary (cognitive) users and primary (license-holding) users by performing distributed beamforming design and rate allocation for the secondary users to maximize a minimum weighted secondary rate; and granting simultaneous spectrum access to the primary and secondary users subject to one or more co-existence constraints.

Abstract: An electronic device substrate having: a base material formed of a thin board; an electrical insulation layer formed on the base material and having plural openings in a thickness direction thereof; and a metal plating layer filled in the plural openings. The base material has a metal layer, a release layer formed contacting the metal layer, and a metal film formed contacting the release layer.

Abstract: Disclosed is a receiver so adapted that even it receives a signal having the same communication frequency and frequency band as its own, restart of a receive-signal processor is inhibited for a fixed period of time if the receive signal is not a desired signal. The result is a reduction in power consumption. The receiver includes a start circuit for detecting a radio-frequency signal and outputting a start signal if a level of the detected radio-frequency signal is no less than a fixed level, and a receive-signal processor for receiving the start signal and starting a demodulating operation for demodulating the radio-frequency signal.

Abstract: A pseudo-random number generation device having a resistance against attack methods that use the number of operations of an LFSR, a stream encryption device, and a program are provided. The stream encryption device has: means (delay means 811 to 81N) which exclusively operate with each LFSR (801 to 80N) in the pseudo-random number generator, that is of a clock control type, and makes uniform the generation processing time or the power consumption of one output unit; or means which randomizes the generation processing time or the power consumption power of one output unit.

Abstract: A method of learning discriminant function for predicting label information by using computer includes: receiving training data including attribute data and label information, to create an initial prediction model based on the attribute data and the label information; calculating, based on the initial prediction model used as a discriminant function, a gradient of a loss function, which is differentiable with respect to the discriminant function and satisfies a monotonous convex function, from the discriminant function and the label information; creating a prediction model from the attribute data and the gradient while assuming that the gradient is label information of each sample of the training data; and updating the discriminant function based on the created prediction model.

Abstract: In order to solve a problem in a conventional semiconductor device that improvement of resistance to electrostatic discharge damage or improvement of an area efficiency is severely restricted, there is provided a semiconductor device including: a first protection diode (DP) having an anode which is connected to a signal wire connected to an I/O pad (PAD), and having a cathode which is connected to a power supply wire (VDD); a power clamp circuit (10) connected between the power supply wire (VDD) and a ground wire (GND); a slot in which a set of the I/O pad (PAD) and the first protection diode (DP) is formed; and a power clamp circuit formation region in which the power clamp circuit (10) is formed, in which the power clamp circuit formation region has a side adjacent to a plurality of the slots, and has a width (W2) larger than a width of the slot.

Abstract: An operation for forming a trench after forming a via hole includes an operation for exposing a region for forming the via hole to light and an operation for exposing a region for forming the interconnect trench. More specifically, even if chemically amplified resist is buried in the via hole after the via hole is formed, then the region for forming of via hole is exposed to light again, so that the inside of the via hole is fully exposed to light. This allows removing the buried resist from the regions in via hole exposed to light, or namely the region and the region, with a developing solution, exposing at least a portion of the inner wall of the via hole to obtain the trench having a desired structure.

Abstract: A voltage-controlled oscillator comprises an inductor and a group of variable capacitance elements forming a resonance circuit. The group of variable capacitance elements includes first and second variable capacitance elements connectable in parallel and having mutually different absolute values of a ratio of control-voltage sensitivity to capacitance. The first and second variable capacitance elements both have a first end supplied with a control voltage for controlling resonance frequency of the resonance circuit and have a second end selectively connected to the inductor by a band selection signal for deciding a band in which the resonance frequency exists.

Abstract: A semiconductor integrated circuit apparatus includes an internal logic circuit unit, a first memory, a second memory and a control circuit unit. The internal logic circuit unit includes scan chains which test circuit normality. The first memory is accessed by the internal logic circuit. The second memory stores valid bits associated with the first memory, wherein the valid bits indicates one of validity and invalidity of data stored in the first memory. The control circuit unit saves internal state data stored in the scan chains to the first memory, and resets the internal state data saved in the first memory to the scan chains.

Abstract: A mask inspection system 10 inspects an inspection object pattern while comparing an inspection object data obtained in such a way as to image the inspection object pattern with a reference pattern data. The mask inspection system 10 is provided with an inspection information preparing part 12 producing inspection algorithm and inspection sensitivity to the reference pattern data based on wafer simulation, a converting part 13 generating a reference graphic data with inspection information while adding the inspection information to the reference graphic data, and a defect judging part 16 judges propriety of an inspection object pattern data while comparing reference graphic data with an inspection object data in every pixel based on the inspection information added to the reference graphic data with inspection information.

Abstract: Disclosed are an apparatus and a method for the adjustment time for IQ offset of a quadrature modulator of a transmission circuit. In adjusting the I-offset and the Q-offset of a quadrature modulator, supplied with an I-signal and a Q-signal output from an analog baseband unit to modulate a carrier. Set-up values of the I-offset and the Q-offset, associated with at least three different points on an IQ offset correction plane having an I-component and a Q-component as X- and Y-coordinates, are set for the analog baseband unit at respective different set-up timings. The values of the carrier leak level, associated with three-point offset set-up values of the output signal of the quadrature modulator, are acquired by a sole measurement operation.

Abstract: A DGP, upon detecting the occurrence of a fault in an IOP that controls a CH, causes another IOP that can control the CH to control the CH and reports to an EPU the occurrence of the fault in the CH and the recovery from the fault. The DGP stores information in a CH configuration table indicating that the other IOP is controlling the CH. Upon receiving the reports of the occurrence of the fault in the CH and the recovery, the EPU refers to the CH configuration table, verifies that the other IOP is controlling the CH, and provides data transfer instructions to the other IOP.

Abstract: A skill authentication server publicizes a home page for test question creation over a communication network. The skill authentication server transmits a home page for a test question creation information input screen to a shop terminal, upon an access from the shop terminal, and receives the screen input information from the shop terminal to create a home page for skill authentication test questions. The shop terminal generates the skill authentication result that becomes the content of an ID card of the customer on the basis of the test answer information from a customer terminal that is input into the home page for skill authentication test questions, and transmits it to a card company server and the shop terminal. The customer inserts the ID card including the skill authentication result into the shop terminal and accepts a guidance suitable for the skill authentication result.

Abstract: Disclosed is a differential amplifier which includes first and second input terminals, an output terminal, first and second differential pairs, and first and second current sources for supplying currents to the first and second differential pairs. The first differential pair has first and second inputs of an input pair connected to the first input terminal and the output terminal, respectively. The second differential pair has first and second inputs of an input pair connected to the second input terminal the output terminal, respectively.

Abstract: A server proxy (12), which is arranged between a distribution server (11) and a router (13a), adds quality information to a packet (19a) from the distribution server (11) to output a packet (19b). A plurality of reception terminal proxies (17a-17n), which are arranged immediately before respective reception terminals (18a-18n), remove the quality information from the packet (19b) distributed via a network (14) and routers (13b-13m), and distribute only necessary information to the respective reception terminals (18). Each reception terminal proxy (17) which includes a quality information acquisition unit (17A) acquires the quality information to transmit, from a quality information calculation/transmission unit (17B), the quality information (51) to an accumulation server (15). The accumulation server (15) saves, in a quality information database, packet quality information (52) for each reception terminal (18).

Abstract: An upper unit and lower unit are connected by two hinge portions that allow them to move between open and closed positions and to turn around each other. Undercuts are formed on an edge of the upper or lower unit and extensions are formed on the lower or upper unit not provided with undercuts, to mate with the undercuts of the other unit. For the upper unit to turn around the lower unit, the upper unit must first be raised so as not to touch the extensions. Therefore, the present invention prevents scraping damage of surfaces of the upper and lower units.

Abstract: A semiconductor device is composed of: an array of CMOS primitive cells provided in a circuit region; a power supply line extended along the array of the CMOS primitive cells and connected to the CMOS primitive cells; a ground line extended along the array of the CMOS primitive cells and connected to the CMOS primitive cells; a first decoupling capacitor provided under the power supply line; a second decoupling capacitor provided under the ground line. The first decoupling capacitor is formed of a PMOS transistor having a gate connected to the ground line. At least one of the source and drain of the PMOS transistor is connected to the power supply line. The second decoupling capacitor is formed of an NMOS transistor having a gate connected to the power supply line. At least one of the source and drain of the NMOS transistor is connected to the ground line.

Abstract: A tunnel junction light emitting device according to the present invention is provided with an active layer and an electron tunneling region supplying the active layer with carriers. The electron tunneling region has a first p-type semiconductor layer, a second p-type semiconductor layer and an n-type semiconductor layer. The second p-type semiconductor layer is sandwiched between the first p-type semiconductor layer and the n-type semiconductor layer, and the first p-type semiconductor layer, the second p-type semiconductor layer and the n-type semiconductor layer form a tunnel junction to which a reverse bias is applied. An energy level at a valence band edge of the second p-type semiconductor layer is equal to or lower than an energy level at a valence band edge of the first p-type semiconductor layer.

Abstract: A monitoring terminal device is provided which is capable of reducing its power consumption to a minimum and of being fully operated even indoors by using a solar cell as a power source. In the monitoring terminal device including a sensor unit and a transmitting unit having a wireless communication function to transmit, by wireless, a sensor monitoring output, the sensor and wireless transmitting unit are activated intermittently, and, when the monitoring terminal device is not operating, supply of power to the sensor unit and transmitting unit is stopped and a control processor is put into a sleep state, which enables reduction of power consumption to a minimum. This ensures a long operation of the monitoring terminal device even in an environment in which power is not supplied from the outside.

Abstract: A semiconductor device includes: a first memory; and a second memory. The first memory includes: a first memory cell array configured to be divided into a plurality of sectors, an erasure time setting register configured to hold a sector erasure assurance time to assure an erasure time for erasing data stored in one sector, and a first control circuit configured to execute a sector erasure test in which data stored in at least one selected sector selected from the plurality of sectors are erased within the sector erasure assurance time. The second memory includes: a second memory cell array configured to have a data storage system different from that of the first memory cell array, and a second control circuit configured to execute a data hold test with respect to the second memory cell array while the sector erasure test is executed.