Abstract: An information processing device includes an instruction fetch unit, an instruction buffer, an instruction executing unit, and an instruction fetch control unit. The instruction fetch unit supplies a fetch address to an instruction memory. The instruction buffer stores an instruction read out from the instruction memory. The instruction executing unit decodes and executes the instruction supplied from the instruction buffer. The instruction fetch control unit stops supply of the fetch address to the instruction memory by the instruction fetch unit when the fetch address corresponds to a first address or an address after the first address while the instruction executing unit executes loop processing. The loop processing is repeatedly executed for a predetermined number of times in accordance with decoding of the loop instruction by the instruction executing unit. The first address is an address after an address of an end instruction included in the loop processing.

Abstract: A radical compound may be used as an active material for an anode layer 2 to provide a novel stable secondary battery with a higher energy density and a larger capacity. The radical compound used has, for example, a spin concentration of 1021 spins/g or more.

Abstract: A semiconductor device, in which it is possible to maintain high reliability in that interfacial breakdown does not occur between a solder ball and a conductive film, is provided. The semiconductor device according to the present invention comprises an uppermost layer interconnection 101, an insulating film, which is provided above the uppermost layer interconnection 101, provided with a pad via 104 reaching the uppermost layer interconnection 101, and a conductive film, which is connected to the uppermost layer interconnection 101 in a bottom of the pad via 104, and formed across from the bottom of the pad via 104 to outside the pad via 104; wherein the conductive film and the solder ball 108 provided in contact with the insulating film, and an alloy layer 110 containing a metallic element contained in the solder ball 108 and a metallic element contained in the conductive film intervene, and the solder ball is formed so as to cover the alloy layer 110.

Abstract: In a protection circuit of an input/output terminal I/O, three types of PNP bipolar transistors are included. In a first PNP type bipolar transistor 10A, the emitter thereof is connected to the input/output terminal I/O, the base thereof is connected to a high-potential power supply terminal VDD, and the collector thereof is connected to a low-potential power supply terminal VSS. In a second PNP type bipolar transistor 10B, the emitter thereof is connected to the input/output terminal I/O, and the base and the collector thereof are connected to the high-potential power supply terminal VDD. In a third PNP type bipolar transistor 10C, the emitter thereof is connected to the low-potential power supply terminal VSS, and the base and the collector thereof are connected to the high-potential power supply terminal VDD.

Abstract: A multiprocessor system includes a plurality of microprocessors configured to operate on a plurality of operating systems, respectively, and a memory section configured to have a plurality of memory spaces respectively allocated to the plurality of microprocessors. Each of the plurality of microprocessors may include a translation look-aside buffer (TLB) and a page table register. The TLB stores a copy of at least a part of data of one of the plurality of memory spaces corresponding to the microprocessor, and the copy includes a relation of each of virtual addresses of a virtual address space and a corresponding physical address of a physical address space as the memory space. The page table register refers to the TLB in response to an execution virtual address generated based on an application program to be executed by the microprocessor to determine an execution physical address corresponding to the execution virtual address.

Abstract: A method for manufacturing a semiconductor device includes: sequentially depositing a gate insulating film 104 composed of a high dielectric constant film containing one or more metallic element(s) selected from a group consisting of Hf, Zr, Al, La and Ta, a barrier film 106 composed of one or more metal nitride selected from a group consisting of TiN, TaN and WN, a metallic film 108 and a polycrystalline silicon film 110 on the semiconductor substrate (p-type semiconductor substrate 102a) to form a multiple-layered film; and silicidizing a lower portion of the polycrystalline silicon film 110 to form a lower layer (forming a first silicide layer 110a) by conducting a heat treatment of the multiple-layered film to diffuse the metal of the metallic film 108 into the polycrystalline silicon film 110.

Abstract: A communication quality controller can avoid, when periodically changing noise is abruptly occurring, disconnection of a communication line used for data communication and prevent resetting of a link speed for the data communication. During the data transmission at a beforehand set link speed, a CRC error counter monitors for a predetermined period of time whether or not an error occurs in a CRC error detector at a period less than a noise period changing periodically. According to presence or absence of the error taking place during the monitoring by the counter, a periodic noise detector determines presence or absence of a periodic noise period abruptly taking place. If presence of the periodic noise is determined, disconnection of an associated communication line is avoided, and after the occurrence of the periodic noise is terminated, the data communication is conducted at the link speed.

Abstract: In a nonvolatile semiconductor memory device, a memory cell array has a plurality of nonvolatile memory cells arranged in a matrix. A selecting section selects as selection memory cells, at least two of the plurality of nonvolatile memory cells from the memory cell array. A write section applies to the selection memory cells, a gate voltage which increases step by step, until a threshold voltage of each of the selection memory cells reaches a target threshold voltage, such that the threshold voltage increases step-by-step.

Abstract: A semiconductor device includes a silicon substrate, a strain-inducing layer, a silicon layer, a FET, and an isolation region. On the silicon substrate, the strain-inducing layer is provided. On the strain-inducing layer, the silicon layer is provided. The strain-inducing layer induces lattice strain in a channel region of the FET in the silicon layer. The silicon layer includes the FET. The FET includes a source/drain region, an SD extension region, a gate electrode and a sidewall. The source/drain region and the strain-inducing layer are spaced from each other. Around the FET, the isolation region is provided. The isolation region penetrates the silicon layer so as to reach the strain-inducing layer.

Abstract: In a formation method for forming a fine structure in a workpiece (30) containing an etching control component, using an isotropic etching process, a mask (32, 34) having an opening (36) is applied to the workpiece, and the workpiece is etched with an etching solution (38) to thereby form a recess (40), corresponding to a shape of the opening, in a surface of the workpiece. The etching of the workpiece is stopped due to the etching control component eluted out of the workpiece in the etching solution within the recess during the isotropic etching process.

Abstract: A thermal stress resistance evaluating method of a semiconductor device includes: forming a test circuit on a corner of each of unit regions arranged on a wafer in an array arrangement; forming a TEG chip by dicing a TEG chip region which is determined by grouping at least two of the unit regions in a predetermined shape; assembling a packaged TEG chip from the TEG chip; and executing a temperature cycling test on the packaged TEG chip by using the test circuit on the TEG chip. According to such a configuration, by adjusting the predetermined shape, the packaged TEG chip of various sizes can be formed in accordance with the design of the product chip size.

Abstract: A communication transfer apparatus and a communication transfer method can transfer communications at low cost without the need of requesting a global IP network to switch any port number. The local internet protocol address of the origin terminal of transfer described in a record relating to a transfer out of the records of the masquerade table that is utilized for an internet protocol masquerade is rewritten as the local internal protocol address of the destination terminal of transfer, while maintaining the global port number of the record.

Abstract: A one-chip type magnetic sensor is provided in which thin-film anisotropic magnetoresistance elements are formed on an IC substrate. Applied magnetic fields can be detected in the magnetic sensor in vertical and horizontal directions, and detection sensitivity can be adjusted with respect to direction. The influence on a magnetic-sensitive property can be suppressed when another magnetic field is applied from another direction. A semiconductor substrate, lead frame, and lead frame(s) are accommodated in a package in the magnetic sensor. Thin-film magnetoresistance elements are formed on the substrate, which includes an electric circuit having comparison and amplification functions. The lead frame is used to mount the semiconductor substrate thereon. The lead frames are connected to the semiconductor substrate, which is attached to a semiconductor attachment surface.

Abstract: It is an object of the present invention to provide a semiconductor apparatus for solving a trade-off between the area, power consumption, noise and accuracy of correction of a variation correction circuit that corrects variations in resistance and threshold voltage, etc. The present invention comprises a multi-value voltage generation circuit shared by a plurality of reading circuits, a multi-value voltage bus that supplies multi-value voltages to the reading circuits and switches that select a voltage suited to variation correction from multi-value voltages, wherein the multi-value voltages are distributed from the multi-value voltage generation circuit to the plurality of reading circuits, the switches select an optimum voltage for correction in the respective reading circuits to thereby correct variations in the elements.

Abstract: Picture and speech communication between plural terminals connected to different networks, such as a circuit-switched network and IP network. A converting apparatus 400 for control information or media information for picture/speech communications is provided across first and second terminals 301, 302 connected to respective different types of networks. Converting apparatus 400 includes control information converter 420, transcoder 450 and ability information converter 460. In case the ability information extracted from the decoding information, received from the first terminal 301, is not coincident to the ability information extracted from the call control information received from the second terminal 302, it is further checked whether or not there is picture format size coincidence. If the picture format size coincidence persists in one direction, processing is carried out for converting part of the decoding information or the control information, without causing the operations of the transcoder.

Abstract: In an authentication apparatus 300, so as to confirm whether a user is legitimate in supplying key information to a resource 500, discernment information for identifying the user is caused to be input, and only in a case where this discernment information coincided with the stored discernment information of the user, the key information is supplied to the resource. Also, in causing the authentication apparatus 300 to register the discernment information of the user, the discernment information is caused to be input, this discernment information is collated with the discernment information registered in a key information management center 200, and in a case where it coincided, the authentication apparatus 300 is caused to register the discernment information.

Abstract: In an optical disk recording method of recording data onto a recordable optical disk which includes a data zone where data is recorded and a management data zone where management data indicating the recorded part of the data zone is recorded, an extended management data zone in which the management data is to be recorded is set in the data zone in response to an extension instruction.

Abstract: A multipath routing architecture for large data transfers is disclosed. The architecture employs an overlay network that provides diverse paths for packets from communicating end hosts to utilize as much capacity as available across multiple paths while ensuring network-wide fair allocation of resources across competing data transfers. A set of transit nodes are interposed between the end-hosts and for each end-to-end connection, a transit node can logically operate as an entry gateway, a relay or exit gateway. Packets from the sender enter the entry node and go to the exit node either directly or through one of a plurality of relay nodes. The exit node delivers the packets to the receiver. A multipath congestion control protocol is executed on the entry node to harness network capacity for large data transfers.

Abstract: Disclosed are an optical element holder and an optical communication module. The optical element holder comprises a pedestal having a pair of fixing sections, a pair of holding sections and a stress-suppressing section. The fixing sections are formed in opposing end portions of the pedestal for being welded to a carrier. The holding sections are formed to face the pedestal in an inner position than positions where the fixing sections are formed so as to hold the optical element by pinching it therebetween. The stress-suppressing section prevents a welding stress, which is generated when the fixing sections are welded to the carrier, from affecting the holding sections.

Abstract: A level conversion circuit includes an input section configured to receive a first signal of a first signal level and a correction signal and generates a second signal of a second signal level from the first signal and the correction signal. A level converting section converts the second signal into an output signal of a third signal level, and a duty correcting section generates the correction signal corresponding to a duty ratio of the output signal and outputs the correction signal to the input section.