Abstract: A DLL circuit includes a first delay line circuit, a first phase comparison circuit, a control circuit, and a first selecting circuit. The first delay line circuit can change a delay amount and provide a delay to a first clock signal. The first phase comparison circuit can detect a phase difference between the first clock signal and an output signal of the first delay line circuit, and a phase difference between a test clock signal of which frequency is lower than the first clock signal and an output signal of the first delay line circuit or a signal after dividing the output signal. The control circuit controls a delay amount of the first delay line circuit according to the detection result of the first phase comparison circuit.

Abstract: Disclosed is a backlight unit which illuminates a display panel from a rear surface thereof, including at least: tubular lamps arranged in parallel to the panel; and a reflecting member which reflects light from the lamps toward the panel, wherein the reflecting member is divided into a first region opposed to an area near an electrode provided in an end portion of the lamp and a second region nearer to a middle area than the first region, the first region having a higher reflectance than the second region. In another backlight unit, a reflecting member is divided, with respect to the arrangement direction of the lamps, into an end lamp near region which is opposed to a lamp arranged in end portion and a middle region which is nearer to a middle area than the end lamp region, the end lamp region having a higher reflectance than the middle region.

Abstract: A semiconductor chip of the present invention has a wiring substrate and a chip part. The wiring substrate has an insulating resin layer having a first major surface and a second major surface, and a first wiring layer disposed on the insulating resin layer on the second major surface side. The chip part has a projection electrode on the bottom surface. The insulating resin layer holds the chip part such that the bottom and side surfaces of the chip part are in contact with the insulating resin layer, and the top surface of the chip part is exposed on the insulating layer on the first major surface side. The projection electrode of the chip part is connected with the first wiring layer.

Abstract: A semiconductor circuit has a plurality of MISFETs formed with channel films comprised of semiconductor layers on an insulation film. Channel film thicknesses of each MISFET are different. A correlation relationship is fulfilled where concentration per unit area of impurity contained in the channel films becomes larger for MISFETs of a thicker channel film thickness. As a result, it is possible to suppress deviation of threshold voltage caused by changes in channel film thickness. In this event, designed values for the channel film thicknesses of the plurality of MISFETs are preferably the same, and the difference in channel film thickness of each MISFET may depend on statistical variation from the designed values. The concentration of the impurity per unit area is proportional to the channel film thickness, or is a function that is convex downwards with respect to the channel film thickness.

Abstract: In order to improve the light transmissivity above the transparent comb-teeth electrodes provided in an in-plane switching mode active matrix liquid crystal display unit, the liquid crystal gaps above the transparent comb-teeth electrodes are made larger than the liquid crystal gaps between the transparent comb-teeth electrodes.

Abstract: A voltage reference circuit is provided with: an operational amplifier circuit; first and second resistor elements; first and second diodes; and first and second transistors. The first resistor element and the first diode are connected in series between a first input terminal of the operational amplifier circuit and a reference level node. The second resistor element and the second diode are connected in series between a second input terminal of the operational amplifier circuit and the reference level node. The first transistor is connected between a power supply node and the first input terminal of the operational amplifier circuit and has a control electrode receiving an output of the operational amplifier circuit. The second transistor is connected between the power supply node and the second input terminal of the operational amplifier circuit and has a control electrode receiving the output of the operational amplifier circuit. The value of R12·ln(n11·n22)/(R12·n12·R11) is adjusted to approximately 23.

Abstract: A first metal film mainly including Ta is formed on a gate insulating film in a region excluding an n MOS transistor formation region and then a polysilicon film is formed to cover the gate insulating film and the first metal film. A first dummy electrode is formed by selectively removing the gate insulating film and the polysilicon film by etching, and a second dummy gate is formed by selectively removing the gate insulating film, the first metal film and the polysilicon film. An insulating layer is formed to embed the dummy gate electrodes and to expose an upper surface of the dummy gate electrodes. The polysilicon film of the dummy gate electrodes is removed to form recesses in the insulating layer, then a second metal film is formed within the recesses and on the insulating layer, and the second metal film is selectively polished.

Abstract: A semiconductor device is provided with a plurality of semiconductor chips and at least one transmission coil (108) for transmitting signals by using inductor coupling between the semiconductor chips. A plurality of transmission coils are connected in series.

Abstract: A display panel driver includes: a compression circuit, when receiving image data of N×M pixels of a target block, generating compressed image data corresponding to the target block by compressing the image data; an image memory storing the compressed image data; a decompression circuit generating decompressed image data by decompressing the compressed image data from the image memory; and a drive circuit driving a display panel in response to the decompressed image data. The compression circuit selects one of a plurality of compression methods based on a correlation between the image data of the N×M pixels, and generates the compressed image data by the selected compression method.

Abstract: In a data receiving apparatus, a measuring section measures a first pulse width of a first pulse, a second pulse width of a second pulse and a third pulse width of a third pulse, during each of which a first signal level of a reception signal is continuous. The first pulse, the second pulse, and the third pulse are sequentially and continuously received by putting a portion of a second signal level different from the first signal level between the first and second pulse and the second and third pulse. A first comparing section performs a first determination based on a measured value of the first pulse width and a measured value of the second pulse width, and the first determination is that the first pulse indicates a start of the reception signal and the second pulse indicates a synchronization signal.

Abstract: A microcomputer that controls an ultrasonic motor includes a storage unit that stores a compare register value, and a digital/analog (D/A) conversion set value, a D/A converter that generates an amplitude control signal with an amplitude value corresponding to the D/A conversion set value, a timer that generates a pulse width modulation (PWM) signal with a frequency corresponding to the compare register value, a central processing unit (CPU) that reads the D/A conversion set value, and the compare register value from the storage unit, and that sets the D/A conversion set value and the compare register value to the D/A converter and the timer, respectively, and an output circuit that generates the control signal with the amplitude of the amplitude control signal, and the frequency of the PWM signal, in response to the amplitude control signal and the PWM signal.

Abstract: A data processing device according to the present invention comprises a nonvolatile memory and a trimming data read control circuit. The nonvolatile memory has a plurality of memory regions in which the same trimming data is stored. The trimming data read control circuit reads the trimming data from a random one of the plurality of memory regions.

Abstract: A radio communication device for receiving a single-carrier signal transmitted in a partial spectrum of Nyquist frequency band, includes: an interference eliminator for eliminating interference from a received signal by spectrum reproduction of non-transmitted spectra using a symbol replica, to output an interference eliminated signal, wherein the interference includes intersymbol interference which is caused by symbols which are more than a predetermined distance away from a decision symbol point; a symbol sequence estimator for estimating a transmission symbol sequence by separating nearby intersymbol interference within the predetermined distance of the decision symbol point based on the interference eliminated signal, to output a decision signal; and a replica generator for generating the symbol replica from decoding result of the decision signal, wherein the symbol replica is fed back to the frequency-domain interference eliminator.

Abstract: A WUSB host (or a WUSB device) transmits a combined information packet and a combined packet to the WUSB device (or the WUSB host). The combined information packet is specified with each packet length of a plurality of packets having a packet length other than a predetermined transfer unit or different packet length. The combined packet is the plurality of packets combined. At this time, the WUSB host transmits the combined information packet to a control endpoint included in the wireless USB device and transmits the combined packet to a bulk OUT endpoint. The WUSB device (or the WUSB host) divides the combined packet into the plurality of packets based on the combined information packet.

Abstract: The invention provides for a method of transmitting data in a mobile radio communications network cell, wherein at least one data block is transmitted, at a first transmission power level, for a user of the cell, the method including the step of monitoring radio resource occupancy within the cell and at least duplicating the said at least one data block within the cell responsive to a determination that the radio resource occupancy has reduced to a level below a threshold value, and whereby the duplicated data blocks are transmitted at a second transmission power level less than the said first transmission power level.

Abstract: A decoding method performs turbo decoding on data that includes a first value before transmission and that includes a second value after received, the second value changed from the first value due to the influence of a transmission path. The decoding method includes performing the turbo decoding on the data to obtain a log-likelihood ratio for the second value, converting the second value to a third value that is obtained by correcting the second value to become closer to the first value when a decoded result from the turbo decoding on the data includes an error and when an absolute value of the log-likelihood ratio is equal to or greater than a predetermined threshold value; and performing the turbo decoding on the data including the third value to obtain a decoded result of the data.

Abstract: A method of performing data equalization in a communication receiver with transmit and receive diversity includes (a) for each i-th receiver antenna and j-th transmitter antenna, calculating a channel response matrix Hi,j from multi-path channel estimates, (b) each i-th receiver antenna, calculating a channel gain matrix Gi from the channel response matrices Hi,j and a scalar noise factor ?, (c) calculating the middle column c0 of Gi?1, (d) calculating a filter coefficient vector wi,j from the middle column c0 of Gi?1 of and the Hermitian transpose Hi,jH of the corresponding channel response matrices Hi,j, (e) filtering input data ri received at each i-th receiver antenna with the corresponding filter coefficient vectors wi,j, (f) despreading the filtered input data from each i-th receiver antenna, (g) applying phase compensation to the despread data, arid (h) combining the despread data from all antennas to obtain received equalized data.

Abstract: A communication apparatus which includes a clock generation circuit outputting a plurality of clocks, each of said plurality of clocks having a different phase from each other; a synchronization detection block receiving a sync word and a payload having a predetermined length after receiving said payload, sampling said sync word by using each of said plurality of clocks and to output a first signal indicating a clock or clocks capable of sampling said sync word successfully, said synchronization detection block being capable of sampling said payload by using a clock or clocks inputted thereinto; a clock phase selection block coupled to said synchronization detection block to-receive said first signal to select one of said plurality of clocks in accordance with said first signal and to output a second signal indicating a selected clock; and a clock gate unit coupled between said clock generation circuit and said synchronization detection block and coupled to said clock phase selection block to receive each of

Abstract: An electronic device substrate having: a base material formed of a thin board; an electrical insulation layer formed on the base material and having plural openings in a thickness direction thereof; and a metal plating layer filled in the plural openings. The base material has a metal layer, a release layer formed contacting the metal layer, and a metal film formed contacting the release layer.

Abstract: The present invention provides methods and systems for building object hierarchy. The method includes: obtaining a set of web pages from a website; conducting an inter-page analysis on the obtained web pages to extract a hierarchy of the web pages; conducting an intra-page analysis on each of the obtained web pages to identify the semantic blocks within the web page and extract a hierarchy of the semantic blocks for all the web pages; and fusing the hierarchy of the semantic blocks with the hierarchy of the web pages to generate a coordinated hierarchy. In one embodiment, the nodes on the generated coordinated hierarchy are then mapped into corresponding objects to generate the coordinated object hierarchy. Compared with the prior arts, the object hierarchy building systems and methods according to the present invention can build the object hierarchy in a more accurate and efficient way by fusing the inter-page analysis result and the intra-page analysis result.