Abstract: A semiconductor device manufactured by forming a plurality of first trenches in each of which a trench gate is formed, in an epitaxial layer of a first conductivity type; implanting an impurity of a second conductivity type into a part beneath each of the first trenches to form a first column region; and implanting an impurity of the second conductivity type into a part beneath a base region formed between the first trenches to form a second column region. The first and second column regions are formed with an impurity concentration such that a total depletion charge in the regions is substantially equal to a depletion charge in the epitaxial layer.

Abstract: An optical backplane includes an optical connector which receives juxtaposed optical signals transmitted in nonparallel to the main surface of a circuit substrate from the circuit substrate or transmits juxtaposed optical signals in nonparallel to the main surface of the circuit substrate to the circuit substrate. The optical connector disposes and accommodates edge portions of a plurality of optical fibers and the disposing direction of the optical fibers in the optical connector is in nonparallel to the main surface of the circuit substrate.

Abstract: A self-refresh control circuit includes a first constant current generating circuit that generates a constant current to change depending on the temperature, a second constant current generating circuit to generate a constant current not depending on the temperature, a current-cycle converting circuit selectively connected to the first constant current generating circuit and the second constant current generating circuit and converting the constant currents inputted from the first constant current generating circuit and the second constant current generating circuit into a test refresh cycle used for setting the refresh cycle.

Abstract: A semiconductor device in which a DRAM and a SRAM are mixedly mounted is provided. The DRAM and the SRAM have a stack-type structure in which a bitline is formed below a capacitive element. A cross couple connection of the SRAM is formed in a layer or below the layer in which a capacitive lower electrode of the DRAM is formed and in a layer or above the layer in which the bitline is formed. For example, the cross couple connection of the SRAM is formed in a same layer as a capacitive contact.

Abstract: A semiconductor device having good production stability and excellent in a contact property between an antireflection film on an Al contained metal film and a conductive plug. The device includes a substrate, an insulating interlayer, and a multi-layer structure. The insulating interlayer is formed in the upper portion of the substrate. The structure is provided on the insulating interlayer. A Ti film, a first TiN film, an AlCu film, a Ti film, a second TiN film, and an etching adjustment film are sequentially formed in the structure. The device includes an insulating interlayer and a conductive plug. The insulating interlayer is provided on the insulating interlayer and the structure. The conductive plug penetrates the insulating interlayer and the etching adjustment film, and an end surface of the conductive plug is located in the second TiN film. The conductive plug includes a Ti film, a TiN film, and a W film.

Abstract: A trace controller receives data access information during load instruction execution and ID (AID) of a load/store buffer to store the data access information during load instruction execution. Then, it generates trace control information TC based on the received data access information and selects a buffer to store the generated trace control information from a plurality of trace control buffers according to the received AID. After that, it receives read data information after load instruction execution and ID (RID) of a load/store buffer used for load instruction execution. Finally, it selects a buffer storing the trace control information TC from the plurality of trace control buffers according to the RID.

Abstract: In a communication system in which a plurality of communication terminals sequentially transfer data to a server during the respective transmission permissible periods assigned to the respective communication terminals, the communication terminal transfers a preamble for synchronization to the server at a time of starting the transmission permissible period, converts a data frame for every 8 bits into every 10 bit-code, and transmits to the server, the signal string with a code indicating the head added there, during the transmission permissible period, and turns a communication to the server into a zero signal state, during a period other than the transmission permissible period, while the server establishes a synchronization by reading the preamble for synchronization inserted into the signal string received from each of the communication terminals, converts a portion of the zero signal state of the signal string into a predetermined special code string, and inversely transforms the received signal string i

Abstract: In one embodiment of the present invention, provided is a semiconductor device having a silicon substrate provided with a DRAM region containing first transistors and capacitor elements, and with a logic region containing second transistors. A minimum gate length of the second transistors provided in the logic region is smaller than a minimum gate length of the first transistors provided in the DRAM region. One of a cobalt silicide layer and a titanium silicide layer is provided on source/drain regions and on gate electrodes of the first transistors provided in the DRAM region, and a nickel-containing silicide layer is provided on source/drain regions and on gate electrodes of the second transistors provided in the logic region.

Abstract: A document delivery server is connected to a user terminal through a network. The document delivery server includes a transmission/reception portion, memory portions that store original document information and public additional information respectively, storage control portions that store and read out the original document information and public additional information together with the memory portions, and a browse information separation/composition portion that transmits the original document information and public additional information to the user terminal through the transmission/reception portion.

Abstract: A toggle magnetic random access memory includes a first memory array, a second memory array and a controller. The first memory array includes a plurality of first memory cells including magnetoresistive elements. The second memory array includes a plurality of second memory cells including magnetoresistive elements and differs from the first memory array in write wirings used for writing. The controller controls the first memory array and the second memory array such that a first state in which a first burst write operation in the first memory array is executed and a second state in which a second burst write operation in the second memory array is executed are alternately executed in a continuous burst write mode. Accordingly, the continuous burst write operation can be executed at the high speed without any drop in the reliability and any increase in the circuit area.

Abstract: Provided is a method of manufacturing an LCD device in which alignment films are formed by a method of printing non-contact alignment films on substrates. Print control patterns are provided between a sealing member and each of display regions. Each of the print control patterns is formed of a highly water-repellent region as well as any one of fine concave structures, fine convex structures and pillar-shaped bodies. The print control patterns control the spreading as liquid of alignment film materials to make the film thickness of each of the alignment film materials uniform.

Abstract: A behavior synthesis apparatus performs a behavior synthesis while optimizing an intermediate point pair, which is equivalent to each other only under a condition to be referenced. When an equivalence condition is provided for an intermediate cone, an equivalence-condition setting unit provides the intermediate cone with the condition for the equivalence. A logic-cone comparison unit determines whether or not the intermediate cone is equivalent under the provided equivalence condition. An intermediate-point-result reflection unit simplifies the intermediate cone with respect to the intermediate point pair determined to be equivalent in the logic cones to be verified. The logic-cone comparison unit checks the equivalence using the simplified logic cone.

Abstract: A light emitting element driving device of the present invention comprises at least one light emitting element and a power supply device for generating a driving current of the light emitting element. The power supply device has a step-up type DC-DC converter circuit. The step-up type DC-DC converter circuit has a soft-start function for gradually increasing the driving current at a rise of the driving current in generation of the driving current. Thus can be provided a light emitting element driving device which is capable of suppressing an inrush current to be generated at turn-on of the main power supply of the power supply device.

Abstract: A display device includes a glass substrate having a display area and a peripheral area. A drive circuit component is mounted on the glass substrate by thermocompression bonding on the peripheral area, and a stress absorption region is provided within the glass substrate close to the circuit component so as to absorb stress produced by thermal deformation of the circuit component. A method of manufacturing the display device of the present invention includes a step of forming stress absorption region into the glass substrate so as to absorb the stress caused by thermocompression bonding of the the circuit component.

Abstract: A method of designing a semiconductor integrated circuit, includes verifying an antenna ratio of a metallic wiring connected to a first gate electrode and the first gate electrode, based on a layout information, and computing a gate area that should be added to avoid a plasma damage to the first gate electrode, based on the verifying. The method further includes modifying a layout of the semiconductor integrated circuit, based on the computing, by arranging a logic cell having a second gate electrode having the gate area or more and is in a state where the logic cell makes no contribution to a logic operation of the semiconductor integrated circuit, in a free region of the layout, and connecting the second gate electrode to the metallic wiring.

Abstract: A first optical receiver circuit in an optical receiver IC, which composes an optical disk device, generates a first voltage signal VS1 indicating an amount of light of a laser beam oscillated in a multimode. A second optical receiver circuit generates a second voltage signal VS2 indicating an amount of light of an optical feedback from an optical disk. A binarization circuit extracts a band component corresponding to a predetermined frequency in VS1, and binarizes the band component, thereby obtaining a digital signal. A delay element delays a phase of the digital signal by time equivalent to a phase difference between VS1 and VS2, and outputs the phase delayed signal as a timing signal. A sample hold circuit (S/H) samples and holds the VS2 in synchronozation with the timing signal. Further, A LPF eliminates a band component corresponding to the frequency from an output signal of the S/H.

Abstract: A semiconductor device includes a MOSFET having: a gate electrode provided over a silicon substrate; and a first impurity diffusion region and a second impurity diffusion region provided in the silicon substrate in different sides of said first gate electrode, wherein the MOSFET has an extension region in an upper section of the first impurity diffusion region and no extension region in an upper section of the second impurity diffusion region, and has a first silicide layer over the first impurity diffusion region and has no silicide layer over the second impurity diffusion region in vicinity of a side edge of the gate electrode.

Abstract: A vapor phase deposition apparatus 100 for forming a thin film comprising a chamber 1060, a piping unit 120 for supplying a source material of the thin film into the chamber 1060 in a gaseous condition, a vaporizer 202 for vaporizing the source material in a source material container 112 and supplying the vaporized gas in the piping unit 120 and a temperature control unit 180, is presented.

Abstract: A power controller includes a digital control circuit which performs a digital control on a basis of a difference between an output voltage supplied to a power control target device and a voltage reference, so that the output voltage is equal to the voltage reference, and a processor control circuit which conducts an operation of a processor in the digital control circuit, in response to a change of a control signal supplied by the power control target device and indicating a state of a load in the power control target device, which monitors an output from the digital control circuit, and which stops the operation of the processor when the load is judged to have no change.

Abstract: Picture and speech communication between plural terminals connected to different networks, such as a circuit-switched network and IP network. A converting apparatus 400 for control information or media information for picture/speech communications is provided across first and second terminals 301, 302 connected to respective different types of networks. Converting apparatus 400 includes control information converter 420, transcoder 450 and ability information converter 460. In case the ability information extracted from the decoding information, received from the first terminal 301, is not coincident to the ability information extracted from the call control information received from the second terminal 302, it is further checked whether or not there is picture format size coincidence. If the picture format size coincidence persists in one direction, processing is carried out for converting part of the decoding information or the control information, without causing the operations of the transcoder.