Abstract: A motion estimator uses many parallel Arithmetic-Logic-Unit (ALU) processors to simultaneously perform searches in many directions from a starting point. Each processor follows a different path outward from the starting point, generating sum-of-absolute differences (SADs) for each point in the path. A best SAD for the path is kept, along with an index into motion vector tables containing X,Y points for all paths. Current and best SAD's, thresholds, and indexes are stored in an ALU dedicated memory. When the number of best SAD's meeting thresholds exceeds a target, the current search-level ends. The index of the overall best SAD locates a new starting point, and a next-denser search-level is performed in the same manner, but over a smaller search area. Each processor calculates SAD's for one 16×16 macroblock, four 8×8 blocks, and 16 4×4 blocks and the net best SAD of these 3 types determines partitioning.

Abstract: A graphics system reduces fetching from memory of color-key pixels when video pixels from a video-overlay window are displayed. A frame buffer is divided into multi-line, multi-pixel blocks that are arranged in block-rows and block-columns. Each block-row has primary and secondary row indicator bits and each block-column has two column indicator bits. When the primary row indicator bit is cleared, all pixels in the block-row are fetched from a frame-buffer memory. When the primary row indicator is set, a secondary row indicator bit selects either first or second column indicator bits for reading. When the selected column indicator bit for a block-column is set, fetching of pixels from the frame buffer memory is skipped. Instead, dummy color-key pixels are generated and inserted into the pixel stream. These dummy pixels match the color key and cause video pixels to be sent to the display. Memory fetching is reduced.

Abstract: A frame buffer stores X pixels per line and Y lines and is read using a burst of B pixels. The un-rotated image is rotated by 90 degrees for display by writing and reading pixels from a line buffer. The line buffer stores a block of B*Y pixels. The frame buffer is logically divided into X/B blocks that are B pixels wide. Blocks are read from the frame buffer from the bottom line to the top with a burst of B pixels per line. An offset locate pixels to read in the line buffer. The offset is B for the first block, and increases by a factor of B for each block read, but wraps around modulo B*Y?1. Pixels for a next block are written into the line buffer to locations vacated as pixels are read out. The increasing offset re-orders the pixels for the rotated display order.

Abstract: A feature phone has two processors that share a display. The display is attached to an applications processor that has a frame buffer for refreshing the display. A base-band processor also runs programs that generate graphics data that is written to a base-band frame buffer. Updates to the base-band frame buffer are sent through a shared-memory interface to a shared memory, and a shared mailbox is written with the message length, triggering a mailbox-interrupt to the applications processor. The applications processor reads the message from the shared memory and updates a copied frame buffer. An overlay engine uses the copied frame buffer to refresh the display when the base-band processor has the focus, or to refresh a smaller base-band window that covers a portion of the display, leaving the rest of the display area for applications-processor graphics data. Rapid switching between the copied and local frame buffer is possible.

Abstract: Associative processing methods and apparatus are described for processing graphics data for three-dimensional graphic displays, e.g., in three-dimensional games. A texture, which comprises a bitmap image used to apply a design onto the surface of a 3D computer model for 3D graphics display, may be converted to APA (associative processor apparatus) instructions.

Abstract: An object in a video sequence is tracked by object masks generated for frames in the sequence. Macroblocks are motion compensated to predict the new object mask. Large differences between the next frame and the current frame detect suspect regions that may be obscured in the next frame. The motion vectors in the object are clustered using a K-means algorithm. The cluster centroid motion vectors are compared to an average motion vector of each suspect region. When the motion differences are small, the suspect region is considered part of the object and removed from the object mask as an occlusion. Large differences between the prior frame and the current frame detect suspected newly-uncovered regions. The average motion vector of each suspect region is compared to cluster centroid motion vectors. When the motion differences are small, the suspect region is added to the object mask as a disocclusion.

Abstract: Red, Green, Blue (RGB) pixels in a Beyer pattern are converted to YUV pixels by a converter. The converter does not interpolate RGB pixels to fill in missing RGB color values but instead performs interpolation during conversion to YUV. An edge-enhancement filter is applied to the preliminary Y values to generate final Y values with sharpened edges. The final Y values are combined with R or B pixels from the Beyer pattern to generate U and V chrominance values. Since the preliminary luminance Y values are edge-enhanced, and then the edge-enhanced Y values are used to generate the U, V, values, enhancement improves U and V values as well. Rather than use full-frame intermediate buffers, a 7-line RGB buffer, a 5-line preliminary Y value buffer, and a 3-line final Y buffer can be used.

Abstract: A graphics controller system which has a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals, all in the form of a CMOS integrated circuit. The video memory is integrated on the same integrated circuit as the graphics controller; no package pins are required for the memory interface. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

Abstract: A feature phone has two processors that share a key pad for user input. The key pad is attached to a base-band processor and sends an interrupt to a user-hardware-interrupt UHI driver running on the base-band processor when the user presses a key. When a hot switch indicates that the local base-band processor has the focus, a key-press event is sent to the local kernel to be sent to programs on the base-band processor. When the hot switch indicates that a remote applications processor has the focus, a message for the event is written through a shared-memory interface to a shared memory on the applications processor. A shared mailbox is written with the message length, triggering a mailbox-interrupt to the applications processor. A virtual UHI driver running on the applications processor reads the event message from the shared memory and passes key-press information to programs on the applications processor.

Abstract: Bayer-pattern pixels captured by an image sensor have only one of the three primary colors (RGB) per pixel location. Rather than interpolate the Bayer-pattern to generate the missing RGB color components for each pixel location, a direct conversion is performed to YUV pixels. A luminance calculator receives a 3×3 block of Bayer-pattern pixels and generates a luminance (Y) pixel for the center pixel location. Different coefficients are multiplied by each of the 9 Bayer-pattern pixels before summing to produce the center Y pixel, depending on the pattern location. A chrominance calculator first receives a 3×3 block of Y pixels generated by the luminance calculator. The 9 Y pixels are averaged to produce an average luminance. Two red or blue pixels in the 3×3 block are averaged and the average luminance subtracted. Then a constant is multiplied to generate the U and V pixels. Intermediate interpolated RGB avoided.

Abstract: A feature phone has a base-band processor and an applications processor that communicate with each other by emulating an internal Ethernet within the phone. TCP/IP stacks in each processor receive data from high-level applications for transmission to the other processor. Ethernet-emulating drivers are called by the IP layers. An Ethernet-emulating transmit driver writes IP-packet data to a shared memory and sends an interrupt to the other processor, which activates a receive routine that reads the IP packet data from the shared memory and sends it up through the TCP/IP stack. There is no twisted-pair cable or other media since the shared memory acts as the transfer media. A shared mailbox holds the packet length and sends an interrupt to one processor when written, while a general-purpose input-output GPIO module sends an interrupt to the other processor. The internal emulated-Ethernet is entirely within the phone and separate from cellular networks.

Abstract: A graphics system stores graphics data in a dynamic-random-access memory (DRAM) and in a faster static random-access memory (SRAM). A refresh controller reads pixel data from a frame buffer that is usually in the faster SRAM, while one or more video overlay engines read graphics objects from the DRAM. However, large frame buffers may be partially stored in the DRAM. Some of the graphics data read by the video overlay engine may reside in the SRAM. A dual-layer arbiter receives requests from the refresh controller and the overlay engines for access to the SRAM and DRAM. When two requestors request the same memory device, the dual-layer arbiter arbitrates access. However, often the requests are to different memory devices and the dual-layer arbiter can pass the requests through without delay, since separate buses to the DRAM and SRAM can be used simultaneously.

Abstract: A method for bus arbitration comprising assigning priorities changeable with time to requesters of a data bus, and for simultaneous bus requests by more than one requestor, granting usage of the bus to the requester with the highest priority at the time of the bus requests.

Abstract: Memory apparatus including a byte-bank organized in N rows and 8 columns, having a capacity of log2(N) bytes, a log2(N) bit address bus operative to address the byte-bank, an address offset bus operative to generate offsets (e.g., one-bit offsets) to bits of the byte-bank with an address conversion operator, and an adder in operative communication with the address offset bus and the log2(N) bit address bus, the adder operative to add addresses of the byte-bank with the offset generated by the address conversion operator and output a result to the log2(N) bit address. A random access memory array may include a plurality of the byte-banks.

Abstract: A CMOS integrated circuit which has a graphics controller system that has a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with package pin connections.

Abstract: Gamma correction or other power functions are generated for correcting the light intensity for digital pixels. Two levels of mapping of segments are preformed to reduce the total number of segments for a given precision. The range of inputs is divided into successively smaller segments. Each segment is smaller than the next by a factor of 1/a for a first or primary level, or 1/b for a second level of segments. All inputs are mapped or scaled up to the input range of the largest segment in the primary level. Then the largest primary segment is further divided into several second-level segments, and the input is again mapped or scaled into the largest of the second-level segments. Gamma correction is performed on the input scaled into the largest second-level segment. A linear approximation within the largest second-level segment is used.

Abstract: A graphics controller system which has a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals, all in the form of a CMOS integrated circuit. The video memory is integrated on the same integrated circuit as the graphics controller; no package pins are required for the memory interface.

Abstract: Methods of adding and subtracting sets of binary numbers using an associative processor. The inner loop over corresponding bits of the operands is executed in only three machine cycles. Only the carry bit of each loop iteration is carried forward to the next loop iteration. At most five logical operations are used per loop iteration for addition, and at most seven logical operations, of which at most five are binary logical operations, are used per loop iteration for subtraction. In each loop iteration, the second input bit is a direct or indirect argument of at most three logical operations in addition, and of at most four logical operations in subtraction. Each loop iteration includes at least one OR operation and at most two XOR operations.

Abstract: A host writes graphics commands and data to programmable registers through a command FIFO that is read by a graphics controller or BitBlt engine. Rather than write an address and a data value for each register programmed, the host writes one address, one index, and several data values. The address points to an index register. The index is a mapping index word with several multi-bit mapping fields. Each multi-bit mapping field in the index identifies a register to be programmed with one of the data values. Since N bits are used for each mapping field, the mapping field can select one register in a bank of 2N−1 registers. The registers in the bank can be programmed in any order, and registers can be skipped. Since only one index is stored in the command FIFO for programming several registers, less memory space and fewer bus cycles are required.

Abstract: An object in a video sequence is tracked by object masks generated for frames in the sequence. Macroblocks are motion compensated to predict the new object mask. Large differences between the next frame and the current frame detect suspect regions that may be obscured in the next frame. The motion vectors in the object are clustered using a K-means algorithm. The cluster centroid motion vectors are compared to an average motion vector of each suspect region. When the motion differences are small, the suspect region is considered part of the object and removed from the object mask as an occlusion. Large differences between the prior frame and the current frame detect suspected newly-uncovered regions. The average motion vector of each suspect region is compared to cluster centroid motion vectors. When the motion differences are small, the suspect region is added to the object mask as a disocclusion.