Abstract: A graphics controller has a standard RGB graphics pixel path from a graphics memory. A second path from the graphics memory transfers movie-overlay pixels in YUV format. Two pixel muxes are used. Each pixel mux selects either RGB graphics pixels or YUV movie pixels converted to the RGB color space. A first pixel mux loads either the graphics or the movie pixels to a path to the external CRT. A second pixel mux loads either the graphics or the movie pixels to an LCD path leading to a flat-panel LCD display. The pixel muxes can act in unison to display the same image on both the external CRT and the local LCD panel, and the movie pixels may be overlaid as a small window over the graphics data. The pixel muxes can also act separately so that different images are displayed on the external CRT and the local LCD panel. One pixel mux selects the RGB pixels while the other pixel mux selects the converted YUV pixels.

Abstract: A graphics controller uses spread-spectrum techniques to modulate the pixel clock over a range of frequencies, reducing the maximum intensity of EMI emissions. When the clock input to the graphics controller is replaced with a modulated clock, the image on a CRT is distorted. Distortion is avoided by only modulating the clock to the flat-panel LCD interface. The vertical and horizontal timing signals for both the CRT and the LCD are generated from the un-modulated clock. Using the un-modulated clock for these critical timing signals ensures that each horizontal line is displayed for the same period of time. Brighter and dimmer lines are thus avoided. A second embodiment modulates the clocks to the CRT and LCD, reducing emissions for both interfaces. Even the timing signals use the modulated clock. The frequency sweep of the modulated clock is reset at the end of every horizontal line. Thus all lines are displayed for the same period, although the transfer of pixels within a line are modulated.

Abstract: A graphics controller overlays a movie window over the graphics pixel data. Movie pixels are from a movie source and are muxed into the pixel path by a pixel mux near the end of the graphics pipeline. A comparison of the current pixel count to the pixel address of the start and ending boundaries of the movie window controls the pixel mux, which selects either graphics pixels or movie pixels for display to a screen. Since the graphics controller is pipelined, the pixel compare near the end of the pipeline does not restart the graphics pipeline early enough for it to pre-process the graphics pixels. The graphics pipeline does not stop during the movie window but instead performs dummy fetches from the graphics memory to a CRT FIFO in the graphics pipeline. Dummy fetches are fetches of graphics pixels that are not displayed. Since these fetches contain non-displayed pixels, they are not needed except to keep the fetch count counting even during the movie window.

Abstract: A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

Abstract: A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

Abstract: A video sub-system features reduced power consumption by periodically disabling the video controller clocks used for transferring pixel data to a screen. The video clocks are pulsed only when pixel data is being transferred to the screen, during the time that a horizontal line of pixels is being scanned on the screen. The video clocks are not pulsed during the horizontal and vertical blanking periods, when the electron beam in a cathode-ray-tube is being re-traced. The video clocks are also not pulsed during a recovery period for a flat-panel screen. A video memory contains pixel information for the entire screen and is controlled by a memory controller. The memory controller uses a memory clock to transfer all or part of a horizontal line of pixels to a video buffer. The pixel data is then read out of the video buffer to the screen in a serial fashion, synchronized to the video clock.

Abstract: A controller chip has dynamic logic which is driven by a suspendable clock. Power is reduced in a standby mode when the clock to the dynamic logic is stopped. However, power is still applied to the dynamic logic in standby mode so that the dynamic logic can be quickly resumed without the delay of re-charging the power-supply capacitances in the dynamic logic. Stopping the clock to dynamic logic can eventually cause loss of data. A more severe problem than data loss is power consumption. When the clock is stopped to dynamic logic, the isolated nodes leak and eventually their voltages change. When their voltages change by more than a transistor threshold voltage then both the p-channel and n-channel transistors in dynamic logic cells can turn on, forming a direct current paths between power and ground. Thus power consumption can increase dramatically in suspend mode. The isolated dynamic nodes of the dynamic logic are instead recharged periodically during suspend mode.

Abstract: Each touchdown of a probe card during wafer-sort testing of integrated circuits can leave a gouge in the pad metal. These gouges reduce the reliability of any wire bond to that pad as voids can be left in the bond where the gouges are. A second auxiliary test pad is adjacent to the primary bonding pad. This second auxiliary test pad is electrically connected to the primary bonding pad. Thus probes can land on the second auxiliary pad rather than the primary pad. Gouges are made on the second pad rather than the primary pad. This second test pad allows for multiple probing. Multiple probing is needed for testing large embedded memories on large logic chips such as video controllers. The yield of large memories is increased by laser repair. Probing and testing is required both before and after laser repair using a memory test machine. However, a logic test machine is used to test the logic controller portion of the IC, but cannot generate the millions of test vectors needed to fully test the embedded memory.