Abstract: A digital-to-analog converter (DAC) is useful for driving both SVGA display monitors and NTSC TV monitors. The DAC converts 8-bit digital signals to analog voltage for SVGA, but converts 9-bit signals to a wider range of analog voltages for NTSC. Instead of doubling a number of current sources from 255 to 511 for 9-bit conversions, a single least-significant-bit (LSB) current source is added for 9-bit mode. The LSB current source adds one-half of the current that the other current sources do. The LSB current source is disabled for 8-bit mode. The current from the other current sources is doubled for 9-bit mode by adjusting the bias voltage. The bias voltage for p-channel transistors in all the current sources is lowered for 9-bit mode by a bias generator. The bias generator compares a voltage across an external resistor to a band-gap reference and adjusts the bias voltage until the voltage drop across the resistor matches the band-gap reference.

Abstract: A sample-rate converter has a FIFO for buffering input samples. The FIFO is written with an input sample by an input clock synchronized to the input audio stream. The samples are read from the FIFO by a derived clock. The derived clock is generated from an output clock using a nominal ratio of Q/P. Read and write counters for the FIFO are compared. When the write counter is ahead of the read counter by exactly a target amount the derived clock is a ratio of Q/P of the output clock. When the write counter is ahead of the read counter by more than the target, the read rate is increased by accelerating the derived clock to a ratio of (Q+1)/P. When the write counter is ahead of the read counter by less than the target amount, the read rate is decreased by slowing the derived clock to a ratio of (Q-1)/P. An accumulator generates the derived clock by adding Q, Q+1, or Q-1 for each output-clock pulse. Each derived-clock pulse reduces the accumulator by P.

Abstract: The amount of time that a row of pixels in a flat-panel display is illuminated is modulated from frame-to-frame and from row-to-row. Pixels in rows that are on for a longer period of time appear brighter than pixels in rows that are on for shorter periods of time. Such line modulation is combined with frame-rate-cycling (FRC) to dramatically increase the number of gray scales that can be generated for any given number of frames in a FRC cycle, and with phase-offsetting to keep the frame period constant and to reduce flicker. An N-frame FRC cycle that previously generated N+1 gray scales now produces a full 2.sup.N gray scales. The total pixel-on time over the N frame cycle depends not just on how many frames the pixel is on, but on which frames the pixel is on. Since each row in each frame in the FRC cycle is on for a different amount of time, aliasing of the frames is greatly lessened or no longer occurs. A line modulation buffer and speeding up the pixel clock to the panel allow for greater modulation.

Abstract: A portable personal computer (PC) can be connected to a variety of different external CRT monitors. Configuration of each CRT monitor is performed by the graphics display driver software so that the user does not have to re-configure the graphics sub-system every time a different CRT monitor is connected. Auto-configuration of Plug-and-Play monitors occurs by reading configuration information from the monitor itself. For Windows 95, the Plug-and-Play drivers are used for auto-configuration, or for older operating systems the video BIOS display-data-channel functions is used. Older "legacy" CRT monitors that do not support Plug-and-Play are still auto-configured. The vertical refresh rate for each resolution is stored in a default register on the graphics controller chip. The vertical refresh rate from default register is copied to an active refresh-rate register when a legacy (non Plug-and-Play) monitor is detected.

Abstract: A graphics controller uses spread-spectrum techniques to modulate the pixel clock over a range of frequencies, reducing the maximum intensity of EMI emissions. When the clock input to the graphics controller is replaced with a modulated clock, the image on a CRT is distorted. Distortion is avoided by only modulating the clock to the flat-panel LCD interface. The vertical and horizontal timing signals for both the CRT and the LCD are generated from the un-modulated clock. Using the un-modulated clock for these critical timing signals ensures that each horizontal line is displayed for the same period of time. Brighter and dimmer lines are thus avoided. A second embodiment modulates the clocks to the CRT and LCD, reducing emissions for both interfaces. Even the timing signals use the modulated clock. The frequency sweep of the modulated clock is reset at the end of every horizontal line. Thus all lines are displayed for the same period, although the transfer of pixels within a line are modulated.

Abstract: A circuit system for generating phase values and frame counts, particularly adapted for liquid crystal displays is described. The phase values are generated by 8.times.8 matrices, which are formed, in turn, from smaller matrices. The circuit system handles a large number of gray scale levels, 64, which are highly linear in their shading with a reduced possibility of display flicker. Furthermore, the frame count generating circuitry are arranged with respect to the phase values generating circuitry for a highly integrated implementation for color displays.

Abstract: A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

Abstract: A method and apparatus for performing memory array/row scoreboarding in a dynamic access memory (DRAM) having dual bank access. The DRAM of the present invention allows dual simultaneous memory accesses into a memory divided into a plurality of arrays (e.g., 48 arrays). Each array of the DRAM contains a plurality of rows (e.g., 256). Each row of the DRAM contains storage for a certain amount of data bits (e.g., 1024). The DRAM in one configuration contains 1.5 Megabytes of memory. During a dual bank DRAM access, the system allows a first access for pre-opening a row (e.g., a page) of DRAM memory within a first array while simultaneously allowing a second access for reading/writing data to an opened row of another array aside from the first array. The present invention scoreboarding system tracks the rows that are currently open so that immediate read/write accesses can take place.

Abstract: A 3D graphics accelerator operates in parallel with a host central processing unit (CPU). Software executing on the host CPU performs transformation and lighting operations on 3D-object primitives such as triangles, and generates gradients across the triangle for red, green, blue, Z-depth, alpha, fog, and specular color components. The gradients for texture attributes are also generated and sent to the graphics accelerator. Both the graphics accelerator and the CPU software perform triangle edge and span walking in synchronization to each other. The CPU software walks the triangle to interpolate non-texture color and depth attributes, while the graphics accelerator walks the triangle to interpolate texture attributes. The graphics accelerator performs a non-linear perspective correction and reads a texture pixel from a texture map. The texture pixel is combined with a color pixel that is received from the CPU software interpolation of non-texture attributes.

Abstract: A multimedia notebook or laptop personal computer (PC) has an enhanced audio system. An external audio controller in a docking station is connected to the laptop PC's audio system using a digital-audio link. The digital-audio link uses digital signals that have high noise immunity. The high noise immunity allows the digital-audio signals to be routed through the inexpensive docking connector, which has many other noisy, high-speed signals. Dedicated, expensive, noise-prone, and difficult-to-connect analog-audio connectors between the laptop PC and the docking station are eliminated. Analog-digital converter audio CODEC's are placed in both the docking station and in the laptop PC. A master mixer in the laptop PC mixes digital audio from the external audio controller in the docking station with digital audio from an external audio controller inside the laptop PC. The master mixer also connects to a zoom-video audio port and to an internal PCI bus for storing and retrieving audio clips.

Abstract: An associative signal processing apparatus for processing a plurality of samples of an incoming signal in parallel, the apparatus comprising: (a) an array of processors, each processor including a multiplicity of associative memory cells, the memory cells being operative to perform: (i) compare operations, in parallel, on the plurality of samples of the incoming signal; and (ii) write operations, in parallel, on the plurality of samples of the incoming signal; and (b) an I/O buffer register including a multiplicity of associative memory cells, the register being operative to: (i) input the plurality of samples of the incoming signal to the array of processors in parallel by having the I/O buffer register memory cells perform at least one associative compare operation and the array memory cells perform at least one associative write operation; and (ii) receive, in parallel, a plurality of processed samples from the array of processors by having the array memory cells perform at least one associative compare op

Abstract: A fractional divider divides an input by a non-whole number M.N, where M is the integer part and N is the fractional part of the divisor. A delay line generates a group of multi-phase clocks from an input clock. A mux selects one of the multi-phase clocks as a selected clock. The selected clock increments a counter that counts to the integer part M. The selected clock also increments a rotational state machine. The rotational state machine makes the mux select a different one of the multi-phase clocks for the first N clocks so that the phase of the selected clock is rotated for N cycles. When multi-phase clocks having slightly higher delays are chosen, the selected clock's period increases, adding a fraction. When multi-phase clocks having slightly smaller delays are chosen, the selected clock's period is reduced, effectively subtracting a fraction. The delay line is part of a delay-locked loop that compares the phase of the last multi-phase clock to the input clock.

Abstract: A clock generator produces a frequency-modulated clock. A master phase-locked loop (PLL) includes a voltage summer that outputs a voltage to a voltage-controlled oscillator (VCO). The voltage to the VCO determines the frequency of the clock generated. A modulated voltage is subtracted by the voltage summer to produce voltage and thus frequency modulations. This modulated voltage is produced by a second loop that operates as a slave to the master PLL. The slave loop is a voltage-locked loop. The peak amplitude of the modulated voltage is locked to a control voltage of the master PLL. The control voltage is a stable voltage input to the voltage summer that is generated by phase comparisons of the output clock to a reference clock. To overcome the problem of locking to the modulating output clock, phase comparison is performed only at the same point in the modulation cycle, at the beginning of each modulation cycle. Thus modulations do not affect phase comparisons.

Abstract: A method and apparatus is disclosed for a fast, one-dimensional, discrete cosine transform (1D DCT) of eight samples, and for a fast, one-dimensional, inverse discrete cosine transform (1D IDCT) for eight coefficients, requiring five parallel additions, five parallel subtractions and one parallel multiply operation. According to one embodiment, the parallel additions and subtractions are executed by performing a parallel add/subtract operation. The data are manipulated in a processor operable to execute add, subtract and multiply operations on a plurality of pairs of data values in parallel. According to a preferred embodiment of the invention, this processor is an associative memory array, typically consisting of several thousands of memory words. The inherent scalability of the associative memory enables increasing throughput by simply increasing the size of the associative memory, enabling performing the 1D DCT for large numbers of samples.

Abstract: A scan converter receives VGA or SVGA graphics data and outputs NTSC or PAL TV data. The scan converter is integrated inside a personal computer's graphics controller, allowing the digital-to-analog converter (DAC) to be used for either CRT-pixel conversion or TV encoding. The VGA timing is altered to better match with TV scan-conversion. The horizontal rate is not constant but can be increased or decreased during the vertical blanking period. A second register is provided for the total number of pixels in a line during vertical blanking, while a first register contains the total number of pixels in a displayable line not during the vertical blanking period. Since lines with fewer pixels require less time to display, the period of time or rate for blanked lines is changed. An extra horizontal line is added during vertical blanking for every second frame for SVGA conversion to better match the asymmetry of TV standards.

Abstract: Audio sample rates are converted by an arbitrary ratio of Q/P using a two-stage sample-rate converter. One stage is an L-tap low-pass finite-impulse-response (FIR) filter, while the other stage is a linear interpolator. Coefficient storage for the L-tap low-pass FIR filter is dramatically reduced by reducing the effective P factor. The effective P factor is reduced by using two stages, with each stage adjusting the sampling rate by a different ratio. A first stage adjusts the sampling rate by Q0/P0, while a second stage further adjusts the sampling rate by Q1/P1. Q0 and P0 are large integers of about 400 to 700 that differ by one or three; thus the ratio Q0/P0 is very close to one. The linear interpolator stage eliminates or adds one or three samples and smoothes the samples by linear interpolation over the 400 to 700 remaining samples. The FIR filter stage adjusts the sample rate by a ratio of Q1/P1, which is approximately but not exactly Q/P.

Abstract: An audio special-effect is created by a slow phase shift. A series of all-pass digital filters are used to shift the phase of an input stream of digital-audio samples. The amount of phase shift is determined by filter coefficients. The filter coefficients are increased and decreased to sweep the phase shift up and down over a relatively long period of time such as one second per sweep. The filter coefficients must be continuously re-generated by a processor as each sweep occurs. Coefficient generation loads the processor, reducing performance of other programs and user applications. An exact prior-art method requires a division operation for each coefficient generated. Since division operations are slow, the processor is especially burdened by coefficient generation. An approximate method for coefficient generation eliminates the division operation and instead uses a multiply or a simpler shift operation.

Abstract: A graphics controller chip has an integrated graphics memory. A wide data interface is provided to a RAM array storing graphics pixel data in the graphics memory. The wide data interface provides 256 bits of data during normal writes, but in a block-write mode the wide data interface is split into two sections. One section contains 128 bits of data, while a second section contains 128 mask bits. The data is replicated to eight half-width columns in the RAM array, while the mask bits disable writing some of the data to the RAM. Separate byte-mask bits can be provided for disabling bytes during normal mode writes, but these byte-mask bits cause multiple copies of the data to be disabled. Thus the mask bits in the second section are more useful as they can disable any individual byte in any of the eight columns. A block write of 64 2-byte pixels can be performed in a single step, as no color-data register and no mask register is needed.

Abstract: A circuit system for generating phase values and frame counts, particularly adapted for liquid crystal displays is described. The phase values are generated by 8.times.8 matrices, which are formed, in turn, from smaller matrices. The circuit system handles a large number of gray scale levels, 64, which are highly linear in their shading with a reduced possibility of display flicker. Furthermore, the frame count generating circuitry are arranged with respect to the phase values generating circuitry for a highly integrated implementation for color displays.

Abstract: A graphics controller drives a flat-panel display and simultaneously drives an external cathode-ray-tube (CRT) display. Horizontal clock pulses continue to be applied to the flat panel during the CRT's vertical blanking or re-trace period so that the flat panel is not left in a constant state during the entire re-trace period. Leaving the flat panel in a constant state for a long period of time can cause flicker or delayed response immediately after the re-trace period ends. Running the horizontal clocks during the re-trace period can lead to D.C. buildup or rolling flicker, believed to be caused by a polarity-inversion counter in the panel assembly which is not designed to receive additional horizontal clocks beyond the number of lines on the flat panel. D.C. buildup in the flat panel is reduced by adding a high-frequency burst of horizontal clock pulses to the flat panel during the CRT's vertical re-trace period. The burst of clock pulses adjusts the count in the polarity-inversion counter.