Abstract: A phase detector determines a phase error value dependent on the relative phase between a local oscillator signal, used for the system clock, and an input signal received over a PR (a, b, b, a) channel. The error value is used to lock the phase and frequency of an input signal to the phase and frequency of the clock in a phase-lock loop (FIG. 1, not shown). The input signal is sampled at regular intervals in accordance with the local oscillator signal, and the sampled values provided on a line 10. A threshold slicer 22 selects an ideal sample value for a sampling point by comparing the sampled values with thresholds received on threshold inputs 23 to 26. A subtracter 32 determines a difference value which corresponds to a difference between the ideal sample value and the actual sample value for that sampling point. A subtracter 28 and a delay register 29 operate to determine the sense of change to the ideal sample value from a ideal sample value for a preceding sampling point.

Abstract: A graphics system includes an accelerated graphics port (AGP) bus to the graphics accelerator. The graphics accelerator includes a 3D-graphics engine that renders textures, and a local graphics memory. Preferably, the local graphics memory is an embedded DRAM on the graphics-accelerator chip. A portion of the personal computer's main memory is set aside as an AGP memory for storing textures for 3D-graphics rendering. High-level application programs create textures in the AGP memory. A 3D graphics software driver that controls the graphics accelerator manages a texture cache in the local graphics memory. When the high-level application requests that the 3D graphics driver render a texture in the AGP memory, the 3D graphics driver moves the texture to the texture cache. Once the texture has been copied from the AGP memory, over the AGP bus to the texture cache in the local graphics memory, the 3D graphics engine begins rendering the texture.

Abstract: Copy protection support is added to the display driver in a laptop PC. Laptop PCs without any copy protection facilitate illegal copying of optical disks such as digital-versatile disk (DVD), since some laptop PCs now include a TV encoder (scan-line converter) that converts the computer-generated formats such as SVGA to TV formats such as NTSC and PAL. While VCRs cannot make copies of computer formats such as SVGA, a VCR connected to the laptop PCs TV-encoder output can make an illegal videocassette copy of a DVD title. The portability of laptop PCs makes them particularly attractive to video thieves. Some PCs are being equipped with TV encoders with advanced copy-protection features such as MacroVision encoders. The video BIOS determines if the TV encoder is MacroVision compliant and is queried by the display driver when a DVD navigator or player requests MacroVision encoding.

Abstract: A reciprocal generator is useful for perspective correction for 3D graphics. The input range is divided into many sections. A lookup table contains reciprocal outputs for only two of the sections, the smallest-inputs section and the largest-inputs section. Entries in the table for the smallest section contain a base and a scale factor to indicate the reciprocal value. One entry is provided for each possible input value in the smallest section. This provides high precision where the outputs have the largest values, reducing visible distortions caused by relatively small changes in the large output values. Each section is divided into intervals, with one table entry for each interval. For the largest section, each table entry has an initial reciprocal and a slope of a line approximating the reciprocal curve in that interval. Reciprocals for inputs within the interval are calculated by multiplying an offset into the interval by the slope, and then adding to the initial reciprocal for that interval.

Abstract: A net sample is added or removed from an audio sample stream by fading in or out fractional samples over many sample periods. A sample-rate converter has a FIFO that is written with an input sample by an input clock synchronized to the input audio stream. The samples are read from the FIFO by a derived clock. The derived clock is generated from an output clock using a nominal ratio of Q/P. Read and write counters for the FIFO are compared. When the write counter is ahead of the read counter by exactly a target amount the derived clock is a ratio of Q/P of the output clock. When the write counter is ahead of the read counter by more than the target, the read rate is increased by removing one net sample over many sample periods. When the write counter is ahead of the read counter by less than the target amount, the read rate is decreased by adding one net sample over many sample periods.

Abstract: A digital-to-analog converter (DEC) is useful for driving both SVGA display monitors and NTSC TV monitors. The DAC converts 8-bit digital signals to analog voltage for SVGA, but converts 9-bit signals to a wider range of analog voltages for NTSC. Instead of doubling a number of current sources from 255 to 511 for 9-bit conversions, a single least-significant-bit (LSB) current source is added for 9-bit mode. The LSB current source adds one-half of the current that the other current sources do. The LSB current source is disabled for 8-bit mode. The current from the other current sources is doubled for 9-bit mode by adjusting the bias voltage. The bias voltage for p-channel transistors in all the current sources is lowered for 9-bit mode by a bias generator. The bias generator compares a voltage across an external resistor to a band-gap reference and adjusts the bias voltage until the voltage drop across the resistor matches the band-gap reference.

Abstract: A 3D graphics processor has parallel triangle pixel pipelines. One or more triangle setup engine(s) receives triangle primitives from a host or geometry engine and generates vertex color, texture and other attributes as well as their gradients. The triangle setup engine makes available all required triangle data to the triangle pixel pipelines. The triangle pixel pipelines accept the next triangle data on a demand basis, when finished with the previous triangle. Each triangle pixel pipeline has a span engine that generates endpoints along the 3 edges of the triangle where the horizontal lines (spans) intersect. Each triangle pixel pipeline also has a raster engine that receives the endpoints as well as gradients and generates color, texture and other attributes for each pixel along a span between endpoints. The raster engine then composites pixels from these attributes and updates visible pixels in the frame buffer.

Abstract: A cascaded multimedia arbiter and method for arbitrating access to a shared multimedia memory, which is used to store multiple frame buffers for multiple monitors. Other buffers for multimedia agents such as for audio, camera input, digital-versatile disk (DVD) input, and three dimensional (3D) rendering share the same memory. The shared memory allows flexible memory allocation as graphics, audio, and multimedia modes change. Many real-time agents such as for graphics and audio read the memory to fill first-in-first-out (FIFO) buffers. These real-time agents are assigned a fixed slot in a round-robin arbitration. The last or final arbitration slot is used by all non-real-time agents, such as the host, 3D engine, and DVD playback. These non-real-time agents can wait, but need the most bandwidth to maximize performance. The last time slot uses a priority arbiter to grant access in a priority order to the non-real-time agents.

Abstract: A controller chip has programmable registers that control the operation of the controller chip. The controller chip connects to a microprocessor and bus controller through a bus that performs burst cycles. Although only one address (the starting address) is sent over the bus during the burst cycle, multiple data words are sent in the burst. These data words are written to addresses that follow the starting address in a fixed burst sequence. Programmable registers are accessed in an order that is not the fixed burst sequence. The programmable registers are accessed in a non-sequential order in a single burst cycle by using a mapping control word. The starting address is is set to the address of a mapping control register in the controller chip. The mapping control word is sent as the first data word after the starting address. The mapping control word is decoded to determine which of the programmable registers are to be written during the burst cycle.

Abstract: A content-addressable memory (CAM) cell uses only n-channel (NMOS) transistors. A total of six transistors (6T) are used in the cell. Dynamic storage and differential sensing are used. A pair of bit lines carry true and complement data. A word line connected to the gates of pass transistors couples the bit lines to gates of storage transistors. The sources of the storage transistors are grounded. Charge is dynamically stored on the gates of the storage transistors when the pass transistors are turned off. One storage transistor has a gate charged to a high voltage and is thus on, while the other storage transistor has its gate discharged to a low voltage and is thus off. The drains of the storage transistors are connected to a match line through a pair of match transistors. The gates of the match transistors are connected to the bit lines. During a compare operation, the test data and its complement are applied to the bit lines, turning one of the match transistors on and the other off.

Abstract: Indexed registers in controller chips are read in a two-step process. First, an 8-bit write instruction writes an index into an index register in the controller chip. Secondly, a 16-bit read instruction reads both the index register and a data register selected by the index from the index register. When index registers are read in a multi-threaded system, programs in two different threads could access the same index register, each writing a different index into the index register. When another thread over-writes an index written by a current thread, the wrong index and the wrong data are read by the current thread. The current thread detects that the index was overwritten by another thread by extracting the index from the 16-bit read and comparing it to the desired index. When the extracted index mis-matches, the current thread retries, again writing the index and reading back both the index and data.

Abstract: A 3D-graphics engine has several texture maps with different levels of detail (LOD). The largest of the four derivatives of the u,v texture-map coordinates with respect to the x,y screen coordinates determines which LOD texture map to select. Using bi-linear interpolation, the four nearest texture pixels or texels are fetched from the texture map in a texture memory and a weighted-average texel generated. Distortion in space and time can be visible when a triangle transitions from one LOD texture map to the next LOD map. Tri-linear interpolation eliminates this LOD-transitioning distortion by generating weighted-average texels for both the LOD map and for four texels from a next LOD map. Unfortunately the calculational complexity is more than doubled for tri-linear rather than bi-linear interpolation. Tri-linear interpolation is employed only near a transition to a next LOD map. When the derivatives are not near an LOD-map transition, only bi-linear interpolation is performed.

Abstract: An embedded DRAM is incorporated inside a digital-versatile-disk (DVD) playback-controller integrated circuit. Data from the DVD optical disk is written to a data block in the embedded DRAM. Error correction is performed by reading the data block to generate syndromes and over-writing errors in the data block with corrections. Once the data block is corrected, it is copied or moved to a different area of the embedded memory, a host-buffer area. As the data block is moved, de-scrambling is performed to decrypt the data. The re-ordered data is stripped of overhead such as ECC bytes and written to the host-buffer area of the embedded DRAM. A checksum is generated as the data is moved, and the checksum is compared to a stored checksum to ensure that all errors were corrected. The data block in the host-buffer area is then transferred to a host. The embedded DRAM has a very wide data-access width of 16 bytes.

Abstract: A digital-versatile disk (DVD) playback-controller integrated circuit (IC) writes data to a block in an embedded DRAM memory. The memory block has rows and columns. Data read from a DVD optical disk is read in row order. Rather than write the DVD data across the rows in the memory block, the DVD data is accumulated into 16-byte words, and successive 16-byte words are written down a column in the memory block. Each row from the DVD disk is written to a 16-byte-wide column in the memory block. The embedded DRAM has a wide 16-byte interface, so all 16 bytes in a word are written during a single memory-access cycle. All the bytes in the memory block must be read in column-order for column-syndrome generation. Since the row-column ordering is reversed, the column-syndrome generator reads bytes across the memory-block rows. Most of these fetches are DRAM page hits, so access speed is improved for column-syndrome generation.

Abstract: Low-latency arbitration is provided for a super-priority communications device such as modems and ISDN/DSL routers, LAN switches and routers. Phantom arbitration slots are inserted between each pair of permanent slots. When a request from the super-priority agent is received, the next phantom slot is used to service the request. The initial latency is just one slot period rather than the whole arbitration loop. Other phantom slots are skipped until the same phantom slot is again activated at the same point in the arbitration loop during subsequent rounds of arbitration. Thus only the initial latency is reduced; subsequent requests from the super-priority agent are handled just once for each arbitration cycle. The low initial latency allows the communications device to quickly respond to an incoming call. Other real-time agents are assigned a fixed slot in a round-robin arbitration. The last arbitration slot is used by all non-real-time agents.

Abstract: Systems and methods are described for distributed DRAM refreshing. A method of distributed DRAM refreshing includes: refreshing a first row of memory cells in a first array of DRAM memory cells with a first row of sense amplifiers; and then refreshing a second row of memory cells in a second array of DRAM memory cells with a second row of sense amplifiers. The systems and methods provide advantages in that magnitude of power transients (noise) can be reduced. In addition, the performance can be improved when the arrays are arranged in multiple sub-groups.

Abstract: A digital-versatile disk (DVD) controller interfaces to an AT bus using ATAPI commands delivered in command packets. A microcontroller executes firmware routines to control the servo that positions the read head, and reads data sectors from the DVD disk. The microcontroller also performs error correction on the DVD data in a disk buffer. A host state machine is used to interface to the AT bus. State transitions in the host state machine are enabled or blocked by the microcontroller by setting auto-transition bits in a state-control register. The microcontroller can set auto bits to allow the host state machine to automatically receive multi-byte command packets, or to transfer data or send status to the host without microcontroller intervention. The microcontroller also has the option of performing any of these steps manually, such as for more complex ATAPI commands. Overlapping ATAPI commands are allowed when the AT bus is released.

Abstract: A video sub-system features reduced power consumption by integrating a video memory onto the same chip as the video memory controller. The video memory is preferably a small DRAM sufficiently large to store all pixel data for lower resolutions, but insufficient for higher resolutions. At higher resolutions, an external DRAM supplements the internal DRAM. The amount of external DRAM needed depends upon the resolution to be supported. The internal DRAM has a wide data bus and thus high bandwidth, since no external I/O pins are needed. The external DRAM is narrow to minimize pincount and power consumption. Since the external DRAM is slower and lower in bandwidth, pixel data from both internal and external DRAMs are interleaved together for each horizontal scan line. Thus the lower bandwidth of the external DRAM is masked by the high bandwidth of the wide internal DRAM.

Abstract: Frame acceleration is achieved by driving multiple LCD frames to a flat-panel display for each CRT frame. Rather than divide the flat-panel display into an upper and a lower half, the panel is divided into many segments. These are physical segments when the panel is row-addressable so that any segment can be accessed at any time. Virtual segments are used for standard dual-scan panels. A buffer memory receives gray-scale converted pixels and arranges them into segment-blocks. Multiple LCD frames are generated and stored using data acceleration. Frame-rate-cycling (FRC) of these multiple frames is used for gray-scaling. The size of the buffer memory is significantly reduced by organizing the frames into three or more segments since input and output timing can be overlapped, allowing lines to be sent to the panel at a higher rate than received by the buffer. While physical segments are most efficient, virtual segments still reduce memory requirements, especially when the multiple LCD frames are repeated.

Abstract: A content-addressable memory (CAM) cell isolates the gate nodes of pass transistors during a write operation. Select transistors between the word line and the pass-transistor gates are driven high by a column-select signal. The bit lines are precharged low. The word line is driven high to Vcc, and the select transistors drive the pass-transistor gates to Vcc-Vtn. One of the bit lines is then driven high to Vcc while the other bit line is held low. As the bit line swings high, capacitive coupling drives one of the pass-transistor gate nodes higher, above Vcc-Vtn. The select transistor then isolates the gate node from the word line. As the bit line continues to swing high, more coupling drives the gate node above Vcc. The boosted gate-node voltage increases the current drive of the pass transistor, accelerating the write operation. When the word line drop to ground, the select transistors drain the gate nodes, disabling the pass transistors and dynamically storing charge on the gates of storage transistors.