Abstract: An adaptive color enhancer applies different scale factors to different pixels in a digital image. More color enhancement occurs for bright pixels and for dim pixels than for average-intensity pixels. Also, more color enhancement is applied to the more colorful pixels while less color enhancement is applied to dull, less-colorful pixels. Rather than enhance all pixels to the same extent, the bright, colorful pixels are enhanced further than the average. Likewise, dim areas are color enhanced more than average. A calculation unit receives a YUV pixel. The Y value is compared to range limits and a piece-wise-linear (PWL) function generates an intermediate scale factor. The absolute values of the U and V color values are combined to create a colorfulness factor. The colorfulness factor is also used with a PWL function and the intermediate scale factor to generate a final scale factor for that pixel. The final scale factor is then multiplied by the U and V values of the pixel to generate a color-corrected pixel.

Abstract: An associative processor includes a plurality of arrays of content addressable memory (CAM) cells and a plurality of tags registers in a tags logic block. Different tags registers are associated with different CAM cell arrays at will, to support parallel execution of the same or different arithmetical operations on two or more CAM cell arrays, and to support pipelined arithmetical operations by having two CAM cell arrays share a tags register to transfer data from one CAM cell array to another using appropriate compare and write operations. All the CAM cell arrays share the same mask and pattern registers. Preferably, at least one tags register is located physically between two of the CAM cell arrays.

Abstract: A graphics controller for a System-On-a-Chip (SOC) used with a battery-powered device allows for reduced-power display modes. The microprocessor writes to a frame buffer that is a single, contiguous address block in virtual memory. A memory management unit (MMU) translates frame-buffer address to multiple physical blocks. The graphics controller fetches pixels from the multiple physical blocks, including a block in an on-chip memory and a block in an external memory. In a low-power mode, pixels are only fetched from the lower-power on-chip memory and not the higher-power external memory. A smaller display window is defined and pixels outside the window are replaced by dummy data,.eliminating external-memory fetches. The smaller display window falls within the first block in the on-chip memory. Status and other information can be displayed in the smaller display window during stand-by modes, while a full-screen of data is displayed for full-power modes.

Abstract: A digital-camera processor receives mono-color digital pixels from an image sensor. Each mono-color pixel is red, blue, or green. The stream of pixels from the sensor has alternating green and red pixels on odd lines, and blue and green pixels on even lines in a Bayer pattern. Each mono-color pixel is white balanced by multiplying with a gain determined in a previous frame and then stored in a line buffer. A horizontal interpolator receives an array of pixels from the line buffer. The horizontal interpolator generates missing color values by interpolation within horizontal lines in the array. The intermediate results from the horizontal interpolator are stored in a column buffer, and represent one column of pixels from the line buffer. A vertical interpolator generates the final RGB value for the pixel in the middle of the column register by vertical interpolation. The RGB values are converted to YUV. The vertical interpolator also generates green values for pixels above and below the middle pixel.

Abstract: A digital-camera processor receives a stream of mono-color pixels in a Bayer pattern from a sensor. Two lines of the pattern are stored in a 2-line buffer. Red, Blue, and Green interpolators receive a 3×3 array of pixels from the 2-line buffer. The interpolators generate missing color values by interpolation. For green, horizontal interpolation is performed for odd lines, while vertical interpolation is performed for even lines. Horizontal and vertical interpolation is thus alternated with alternate lines. Edge detection is performed at the same time as interpolation, on the green pixels from the 2-line buffer. An edge-detection filter is multiplied by the green pixels in the 3×3 array from the 2-line buffer. Different edge-detection filters are used for odd and even lines. These filters are modified to detect edges running perpendicular to the direction of the green interpolation filter. Edges in the same direction as the interpolation filter are ignored.

Abstract: An incrementer pipelines the generation of carry lookahead signals. Count registers hold a current count of the incrementer. The current count is fed back as inputs to sum logic, which generates sum bits that are latched into the count registers as a next count. All-ones detect logic detects when all lesser-significance bits in the current count are ones. When all lesser bits are ones, the sum logic toggles the count bit to generate the sum bit for that bit position. Pre-carry logic generates pre-carry lookahead signals from the sum bits. The pre-carry lookahead signals are latched into pipelined carry registers. The pipelined carry registers drive pipelined carry lookahead signals to the all-ones detect logic. Thus carry lookahead signals are generated from a prior sum but used in a next clock cycle to generate then next sum.

Abstract: An associative processor uses a content-addressable memory (CAM) array to operate on data. The array has several CAM banks that store data in CAM memory cells. Each CAM bank has a register file that stores compare data that drives compare bit lines to the CAM cells, which activate row-match signals for rows with matching data. Each CAM bank has a register file with copies of compare data for all CAM banks. An index value identifies which of the compare registers drives the bank's compare bit lines. When a bank-swap instruction is executed, the index values of two banks are swapped, causing the compare data to be used for a different CAM bank. The physical data in the CAM banks is not swapped, but the compare data used for comparisons is swapped. Since the register files contain all banks' compare data, the compare data does not have to be physically moved.

Abstract: An Internet imaging device, such as camera, scanner and digital television display, is disclosed. The device combines the advantages of platform-independent page description languages, such as Adobe PostScript 3, with an imaging device that connects directly to remote locations via the Internet. The device outputs image data and image processing commands in a platform-independent page description language via cordless communication such as a cellular phone. The data are transferred directly to remote display units, such as printers and digital televisions, thereby eliminating two personal computers (PCs): one at the input end of the communication and one at the output end. The device taught by the present invention need not include a flash memory or other storage medium, as images are transferred directly when generated.

Abstract: A 3D-graphics engine has several texture maps with different levels of detail (LOD). The largest of the four derivatives of the u,v texture-map coordinates with respect to the x,y screen coordinates determines which LOD texture map to select. Using bi-linear interpolation, the four nearest texture pixels or texels are fetched from the texture map in a texture memory and a weighted-average texel generated. Distortion in space and time can be visible when a triangle transitions from one LOD texture map to the next LOD map. Tri-linear interpolation eliminates this LOD-transitioning distortion by generating weighted-average texels for both the LOD map and for four texels from a next LOD map. Unfortunately the calculational complexity is more than doubled for tri-linear rather than bi-linear interpolation. Tri-linear interpolation is employed only near a transition to a next LOD map. When the derivatives are not near an LOD-map transition, only bi-linear interpolation is performed.

Abstract: A specialized Sum-of-Absolute-Difference (SAD) calculator for motion estimation uses inversion rather than 2's complementing. The absolute-value operation of each pixel-pair difference is performed by a bit-wise inversion rather than a complement. This reduces delay since the adder/incrementer propagation is eliminated. The increment needed to adjust for inversion rather than 2's complementing is accomplished by using the carry inputs to the summing and final adders that generate the sum of the absolute differences. When 2-input final adders are used for summing, a total of k−1 adders are used to sum k absolute differences. One additional increment is needed since only k−1 adders are available. A reduced half-adder rather than a full adder is inserted between the summing and final adder for this remaining increment. Propagation of carries between bit positions in a full adder can be avoided using the half adder.

Abstract: A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

Abstract: A data processing device includes an associative processor that in turn includes an array of content addressable memory (CAM) cells and a plurality of tags registers. The device also includes a memory for storing the data and a bus for exchanging the data with the associative processor. Data are exchanged in parallel, via one of the CAM cell columns, one column of data at a time.

Abstract: An associative signal processing apparatus for processing a plurality of samples of an incoming signal in parallel, the apparatus comprising: (a) an array, of processors, each processor including a multiplicity of associative memory cells, the memory cells being operative to perform: (i) compare operations, in parallel, on the plurality of samples of the incoming signal; and (ii) write operations, in parallel, on the plurality of samples of the incoming signal; and (b) an I/O buffer register including a multiplicity of associative memory cells, the register being operative to: (i) input the plurality of samples of the incoming signal to the array of processors in parallel by having the I/O buffer register memory cells perform at least one associative compare operation and the array memory cells perform at least one associative write operation; and (ii) receive, in parallel, a plurality of processed samples from the array of processors by having the array memory cells perform at least one associative compare o

Abstract: Disclosed is a texture prefetching method for use in a three-dimensional graphics display system in which texture maps of an object are stored in memory for texels at (u,v) memory locations. The method of fetching texels for use in calculating (x,y) display pixel values comprises the steps of: a) identifying in (u,v) space a geometric shape to be displayed in (x,y) space, b) establishing tiles of pixels within the geometric shape for use in accessing texels, c) computing texel addresses at one side of a tile based on current addresses (topuc, topvc) and first and second derivatives of (u,v) as a function of (x) and a first derivative as a function of (y), d) computing texel addresses at an opposing side of the tile based on current addresses (u0,v0) and first and second derivatives of (u,v) as a function of (x) and a first derivative as a function of (y), and e) fetching texel blocks within the tiles as defined by the addresses in steps c) and d).

Abstract: A store-and-forward network switch uses an embedded dynamic-random-access memory (DRAM) packet memory. An input port controller receiving a packet writes the packet to the embedded packet memory. The input port controller then sends a message to the output port over an internal token bus. The message includes the row address in the embedded packet memory where the packet was written and its length. The output port reads the message and reads the packet from the embedded memory at the row address before transmitting the packet to external media. Packets are stored at row boundaries so that DRAM page-mode cycles predominate. Only one packet is written to each DRAM row or page. Thus the column address is not sent between ports with the message sent over the token bus. A routing table can also be included in the embedded DRAM.

Abstract: Digital-video compression uses motion vectors to encode movement of macroblocks from one image to another image in a sequence of images. Motion vectors are estimated using multiple levels of a picture, with higher levels having lower resolutions. Such hierarchical or pyramid motion estimation generates lower-resolution pictures from the full-resolution picture. A selected macroblock in a reference picture is compared to ranges in each successively-higher-resolution level. Rather than store the levels of a picture as full pixels, only a luminance Y component of a YUV pixel is stored and used for motion estimation. Further memory savings is achieved by reducing the width of the Y pixels from 8 bits to 6 bits for the top and bottom levels, and to 4 bits for intermediate levels of the picture. Pixels are reduced in width by storing only the most-significant-bits (MSBs), or by dithering. Motion estimation searches in each level are performed using pictures with reduced-width pixels.

Abstract: A data processing device includes an associative processor that in turn includes one or more arrays of content addressable memory (CAM) cells and two or more tags registers. The device also includes a memory for storing the data and a bus for exchanging the data with the associative processor. During input and output operations, data are exchanged in parallel, via one of the tags registers. Another tags register is used to select rows of CAM cells for input or output. By appropriately shifting the bits in the buffer tags register between write or compare operation cycles, entire words are exchanged between the selected CAM cell rows and the buffer tags register. During arithmetical operations, in an embodiment with multiple CAM cell arrays, different tags registers are associated with different CAM cell arrays at will.

Abstract: A multimedia notebook or laptop personal computer (PC) has an enhanced audio system. An external audio controller in a docking station is connected to the laptop PC's audio system using a digital-audio link. The digital-audio link uses digital signals that have high noise immunity. The high noise immunity allows the digital-audio signals to be routed through the inexpensive docking connector, which has many other noisy, high-speed signals. Dedicated, expensive, noise-prone, and difficult-to-connect analog-audio connectors between the laptop PC and the docking station are eliminated. Analog-digital converter audio CODEC's are placed in both the docking station and in the laptop PC. A master mixer in the laptop PC mixes digital audio from the external audio controller in the docking station with digital audio from an external audio controller inside the laptop PC. The master mixer also connects to a zoom-video audio port and to an internal PCI bus for storing and retrieving audio clips.

Abstract: A CMOS integrated circuit that comprises a graphics controller system that consists of a graphics engine and video memory together with some interface blocks, a PCMCIA host adapter, an infrared interface for generating video images on a LCD or CRT display unit, and a video stream interface for receiving video signals. Since the video memory is integrated on the same integrated circuit as the graphics controller, no package pins are required for the memory interface. The pins thus saved are used to provide access to an on-chip PCMCIA host adapter. The internal memory interface is 128 bits wide. Simultaneous performance improvement and power dissipation reduction is achieved because of the wide memory interface and the elimination of the large parasitic capacitances associated with a package pin connection.

Abstract: A search engine for a network switch reads a routing table for an entry with a matching MAC or IP address. The routing table is contained in an embedded DRAM. The search engine and the embedded-DRAM routing table are integrated together on the same integrated circuit chip, allowing a very wide data path between the search engine and the routing table. A free-running sequencer outputs addresses to the routing table so that each entry is read in a continuous-loop sequence. The same entry is sent to comparators for all active searches. Destination addresses for different input ports are compared to the entry read from the table. A match ends the search for a port while searches for other ports continue. Since ports can begin and end searches at any point in the continuous-loop sequence, a same low latency is provided for all input ports, even when other searches are in progress. The wide data path from the embedded-DRAM allows several entries to be read and compared for each cycle and for each port.