Patents Assigned to Novellus Systems
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Publication number: 20130092086Abstract: A system for reducing parasitic plasma in a semiconductor process comprises a first surface and a plurality of dielectric layers that are arranged between an electrode and the first surface. The first surface and the electrode have substantially different electrical potentials. The plurality of dielectric layers defines a first gap between the electrode and one of the plurality of dielectric layers, a second gap between adjacent ones of the plurality of dielectric layers, and a third gap between a last one of the plurality of dielectric layers and the first surface. A number of the plurality of dielectric layers and sizes of the first gap, the second gap and the third gap are selected to prevent parasitic plasma between the first surface and the electrode during the semiconductor process.Type: ApplicationFiled: November 23, 2011Publication date: April 18, 2013Applicant: Novellus Systems, Inc.Inventors: Douglas Keil, Edward Augustyniak, Karl Leeser, Mohamed Sabri
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Patent number: 8419964Abstract: Chemical etching methods and associated modules for performing the removal of metal from the edge bevel region of a semiconductor wafer are described. The methods and systems provide the thin layer of pre-rinsing liquid before applying etchant at the edge bevel region of the wafer. The etchant is less diluted and diffuses faster through a thinned layer of rinsing liquid. An edge bevel removal embodiment involving that is particularly effective at reducing process time, narrowing the metal taper and allowing for subsequent chemical mechanical polishing, is disclosed.Type: GrantFiled: August 27, 2008Date of Patent: April 16, 2013Assignee: Novellus Systems, Inc.Inventors: Kousik Ganesan, Shanthinath Ghongadi, Tariq Majid, Aaron Labrie, Steven T. Mayer
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Patent number: 8415261Abstract: Methods of forming a capping layer on conductive lines in a semiconductor device may be characterized by the following operations: (a) providing a semiconductor substrate comprising a dielectric layer having (i) exposed conductive lines (e.g., copper lines) disposed therein, and (ii) an exposed barrier layer disposed thereon; and (b) depositing a capping layer material on at least the exposed conductive lines of the semiconductor substrate. In certain embodiments, the method may also involve removing at least a portion of a conductive layer (e.g., overburden) disposed over the barrier layer and conductive lines to expose the barrier layer.Type: GrantFiled: October 11, 2011Date of Patent: April 9, 2013Assignee: Novellus Systems, Inc.Inventors: Jonathan D. Reid, Eric G. Webb, Edmund B. Minshall, Avishai Kepten, R. Marshall Stowell, Steven T. Mayer
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Patent number: 8409985Abstract: The present invention addresses this need by providing methods for depositing low resistivity tungsten films in small features and features having high aspect ratios. The methods involve depositing very thin tungsten nucleation layers by pulsed nucleation layer (PNL) processes and then using chemical vapor deposition (CVD) to deposit a tungsten layer to fill the feature. Depositing the tungsten nucleation layer involves exposing the substrate to alternating pulses of a boron-containing reducing agent and a tungsten-containing precursor without using any hydrogen gas, e.g., as a carrier or background gas. Using this process, a conformal tungsten nucleation layer can be deposited to a thickness as small as about 10 Angstroms. The feature may then be wholly or partially filled with tungsten by a hydrogen reduction chemical vapor deposition process. Resistivities of about 14 ??-cm for a 500 Angstrom film may be obtained.Type: GrantFiled: April 27, 2011Date of Patent: April 2, 2013Assignee: Novellus Systems, Inc.Inventors: Lana Hiului Chan, Kaihan Ashtiani, Joshua Collins
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Patent number: 8409987Abstract: Methods of forming low resistivity tungsten films with good uniformity and good adhesion to the underlying layer are provided. The methods involve forming a tungsten nucleation layer using a pulsed nucleation layer process at low temperature and then treating the deposited nucleation layer prior to depositing the bulk tungsten fill. The treatment operation lowers resistivity of the deposited tungsten film. In certain embodiments, the depositing the nucleation layer involves a boron-based chemistry in the absence of hydrogen. Also in certain embodiments, the treatment operations involve exposing the nucleation layer to alternating cycles of a reducing agent and a tungsten-containing precursor. The methods are useful for depositing films in high aspect ratio and/or narrow features. The films exhibit low resistivity at narrow line widths and excellent step coverage.Type: GrantFiled: September 23, 2011Date of Patent: April 2, 2013Assignee: Novellus Systems, Inc.Inventors: Anand Chandrashekar, Mirko Glass, Raashina Humayun, Michal Danek, Kaihan Ashtiani, Feng Chen, Lana Hiului Chan, Anil Mane
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Patent number: 8398816Abstract: Porogen accumulation in a UV-cure chamber is reduced by removing outgassed porogen through a heated outlet while purge gas is flowed across a window through which a wafer is exposed to UV light. A purge ring having specific major and minor exhaust to inlet area ratios may be partially made of flame polished quartz to improve flow dynamics. The reduction in porogen accumulation allows more wafers to be processed between chamber cleans, thus improving throughput and cost.Type: GrantFiled: June 3, 2008Date of Patent: March 19, 2013Assignee: Novellus Systems, Inc.Inventors: Lisa Gytri, Jeff Gordon, James Lee, Carmen Balderrama, Joseph Brett Harris
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Patent number: 8398831Abstract: Embodiments of a closed-contact electroplating cup assembly that may be rapidly cleaned while an electroplating system is on-line are disclosed. One disclosed embodiment comprises a cup assembly and a cone assembly, wherein the cup assembly comprises a cup bottom comprising an opening, a seal surrounding the opening, an electrical contact structure comprising a plurality of electrical contacts disposed around the opening, and an interior cup side that is tapered inwardly in along an axial direction of the cup from a cup top toward the cup bottom.Type: GrantFiled: April 4, 2011Date of Patent: March 19, 2013Assignee: Novellus Systems, Inc.Inventors: Shantinath Ghongadi, Robert Rash, Jeff Hawkins, Seshasayee Varadarajan, Tariq Majid, Kousik Ganesan, Bryan Buckalew, Brian Evans
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Patent number: 8377268Abstract: Embodiments of a closed-contact electroplating cup are disclosed. One embodiment comprises a cup bottom comprising an opening, and a seal disposed on the cup bottom around the opening. The seal comprises a wafer-contacting peak located substantially at an inner edge of the seal. The embodiment also comprises an electrical contact structure disposed over a portion of the seal, wherein the electrical contact structure comprises an outer ring and a plurality of contacts extending inwardly from the outer ring, and wherein each contact has a generally flat wafer-contacting surface. The embodiment further comprises a wafer-centering mechanism configured to center a wafer in the cup.Type: GrantFiled: June 6, 2011Date of Patent: February 19, 2013Assignee: Novellus Systems, Inc.Inventors: Robert Rash, Shantinath Ghongadi, Kousik Ganesan, Zhian He, Tariq Majid, Jeff Hawkins, Seshasayee Varadarajan, Bryan Buckalew
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Patent number: 8377824Abstract: Apparatus and methods for depositing copper on tungsten are presented. The invention finds particular use in the semiconductor industry for depositing copper seed layers onto fields or through silicon vias having tungsten barrier layers, both reducing cost and complexity of existing methods.Type: GrantFiled: April 2, 2012Date of Patent: February 19, 2013Assignee: Novellus Systems, Inc.Inventors: Jonathan Reid, Sesha Varadarajan, Ugur Emekli
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Patent number: 8372757Abstract: Exposed copper regions on a semiconductor substrate can be etched by a wet etching solution comprising (i) one or more complexing agents selected from the group consisting of bidentate, tridentate, and quadridentate complexing agents; and (ii) an oxidizer, at a pH of between about 5 and 12. In many embodiments, the etching is substantially isotropic and occurs without visible formation of insoluble species on the surface of copper. The etching is useful in a number of processes in semiconductor fabrication, including for partial or complete removal of copper overburden, for planarization of copper surfaces, and for forming recesses in copper-filled damascene features. Examples of suitable etching solutions include solutions comprising a diamine (e.g., ethylenediamine) and/or a triamine (e.g., diethylenetriamine) as bidentate and tridentate complexing agents respectively and hydrogen peroxide as an oxidizer.Type: GrantFiled: August 4, 2009Date of Patent: February 12, 2013Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, Eric Webb, David W. Porter
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Patent number: 8371567Abstract: Examples of novel semiconductor processing pedestals, and apparatuses including such pedestals, are described. These pedestals are specifically configured to provide uniform heat transfer to semiconductor substrates and to reduce maintenance complexity and/or frequency. Specifically, a pedestal may include a removable cover positioned over a metal platen of the pedestal. The removable cover is configured to maintain a consistent and uniform temperature profile of its substrate-facing surface even though the platen's upper-surface, which supports the cover and is in thermal communication with the cover, may have a much less uniform temperature profile. The cover may be made from certain ceramic materials and shaped as a thin plate. These materials are resistant to the processing environments and maintain their thermal characteristics over many processing cycles. The cover can be easily removed from the platen and replaced with a new one without a need for major disassembly of the entire apparatus.Type: GrantFiled: April 13, 2011Date of Patent: February 12, 2013Assignee: Novellus Systems, Inc.Inventors: Ivelin Angelov, Brian Severson, Natan Solomon
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Patent number: 8372258Abstract: The working electrode in the flow channel of a flow-through electrolytic detection cell is preconditioned by flowing a preconditioning electroplating solution with preconditioner species through the flow channel while applying a negative potential. Flow of liquid through the flow channel is rapidly switched from preconditioning solution to a target solution containing an organic target solute to be measured. The transient response of the system resulting from exposure of the working electrode to organic target solute is detected by measuring current density during an initial transient time period. An unknown concentration of target solute is determined by comparing the transient response with one or more transient responses characteristic of known concentrations. A preferred measuring system is operable to switch flow from preconditioning solution to target solution in about 200 milliseconds or less.Type: GrantFiled: August 3, 2009Date of Patent: February 12, 2013Assignee: Novellus Systems, Inc.Inventors: Mark J. Willey, Lian Guo, Steven T. Mayer
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Patent number: 8367546Abstract: Novel low-resistivity tungsten film stack schemes and methods for depositing them are provided. The film stacks include a mixed tungsten/tungsten-containing compound (e.g., WC) layer as a base for deposition of tungsten nucleation and/or bulk layers. According to various embodiments, these tungsten rich layers may be used as barrier and/or adhesion layers in tungsten contact metallization and bitlines. Deposition of the tungsten-rich layers involves exposing the substrate to a halogen-free organometallic tungsten precursor. The mixed tungsten/tungsten carbide layer is a thin, low resistivity film with excellent adhesion and a good base for subsequent tungsten plug or line formation.Type: GrantFiled: October 18, 2011Date of Patent: February 5, 2013Assignee: Novellus Systems, Inc.Inventors: Raashina Humayun, Kaihan Ashtiani, Karl B. Levy
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Patent number: 8362571Abstract: Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is PMOS devices using a highly compressive post-salicide amorphous carbon capping layer applied as a blanket over on at least the source and drain regions. The stress from this capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in PMOS channel.Type: GrantFiled: January 28, 2011Date of Patent: January 29, 2013Assignee: Novellus Systems, Inc.Inventors: Qingguo Wu, James S. Sims, Mandyam Sriram, Seshasayee Varadarajan, Haiying Fu, Pramod Subramonium, Jon Henri, Sirish Reddy
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Publication number: 20130000848Abstract: A substrate processing system includes a pedestal including a substrate supporting surface having a diameter that is greater than a diameter of a substrate to be processed by the substrate processing system. A first surface extends a first distance above the substrate supporting surface in a direction substantially perpendicular to the substrate supporting surface. The first distance is greater than or equal to one-half of a thickness of the substrate. A gap is defined between the first surface and an outer diameter of the substrate. A second surface extends a second distance from the first surface at an angle with respect to the first surface. The angle is greater than zero and less than ninety degrees. A third surface extends from the second surface and is substantially parallel to the substrate supporting surface. An etchant source directs etchant onto the substrate to etch the substrate.Type: ApplicationFiled: May 2, 2012Publication date: January 3, 2013Applicant: Novellus Systems Inc.Inventors: Panya Wongsenakhum, Gary Lind, Prashanth Kothnur
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Publication number: 20130005140Abstract: A method for filling a recessed feature of a substrate includes a) at least partially filling a recessed feature of a substrate with tungsten-containing film using at least one of chemical vapor deposition (CVD) and atomic layer deposition (ALD); b) at a predetermined temperature, using an etchant including activated fluorine species to selectively etch the tungsten-containing film more than an underlying material of the recessed feature without removing all of the tungsten-containing film at a bottom of the recessed feature; and c) filling the recessed feature using at least one of CVD and ALD.Type: ApplicationFiled: June 28, 2012Publication date: January 3, 2013Applicant: Novellus Systems, Inc.Inventors: Esther Jeng, Anand Chandrashekar, Raashina Humayun, Michal Danek, Ronald Powell
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Patent number: 8343318Abstract: A physical vapor deposition (PVD) system includes a chamber and a plurality of electromagnetic coils arranged around the chamber. First and second annular bands of permanent magnets are arranged around the chamber with poles oriented perpendicular to a magnetic field imposed by the electromagnetic coils. Each of the permanent magnets in the first annular band is arranged with poles having a first polarity closest to a central axis of the chamber. Each of the permanent magnets in the second annular band is arranged anti-parallel with respect to the permanent magnets in the first annular band.Type: GrantFiled: March 25, 2010Date of Patent: January 1, 2013Assignee: Novellus Systems Inc.Inventors: Karl Leeser, Ishtak Karim, Alexander Dulkin
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Patent number: 8329576Abstract: Methods of improving the uniformity and adhesion of low resistivity tungsten films are provided. Low resistivity tungsten films are formed by exposing the tungsten nucleation layer to a reducing agent in a series of pulses before depositing the tungsten bulk layer. According to various embodiments, the methods involve reducing agent pulses with different flow rates, different pulse times and different interval times.Type: GrantFiled: July 1, 2010Date of Patent: December 11, 2012Assignee: Novellus Systems, Inc.Inventors: Lana Hiului Chan, Feng Chen, Karl B. Levy
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Patent number: D671901Type: GrantFiled: April 13, 2011Date of Patent: December 4, 2012Assignee: Novellus Systems, Inc.Inventors: Ivelin Angelov, Brian Severson, Natan Solomon
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Patent number: D672010Type: GrantFiled: March 16, 2012Date of Patent: December 4, 2012Assignee: Novellus Systems, Inc.Inventors: Percival Verdeflor, Alan Popiolkowski, Evan Patton