Patents Assigned to Novellus Systems
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Patent number: 8481403Abstract: Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manner gaps on the substrate are filled with a solid dielectric material. According to various embodiments, the methods involve reacting a dielectric precursor with an oxidant to form the dielectric material. In certain embodiments, the dielectric precursor condenses and subsequently reacts with the oxidant to form dielectric material. In certain embodiments, vapor phase reactants react to form a condensed flowable film.Type: GrantFiled: January 4, 2011Date of Patent: July 9, 2013Assignee: Novellus Systems, Inc.Inventors: Vishal Gauri, Raashina Humayun, Chi-I Lang, Judy H. Huang, Michael Barnes, Sunil Shanker
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Patent number: 8481432Abstract: An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting.Type: GrantFiled: May 26, 2011Date of Patent: July 9, 2013Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, Daniel A. Koos, Eric Webb
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Patent number: 8475637Abstract: Embodiments related to increasing a uniformity of an electroplated film are disclosed. For example, one disclosed embodiment provides an electroplating apparatus comprising a plating chamber, a work piece holder, a cathode contact configured to electrically contact a work piece, and an anode contact configured to electrically contact an anode disposed in the plating chamber. A diffusing barrier is disposed between the cathode contact and the anode contact to provide a uniform electrolyte flow to the work piece, and electrolyte delivery and return paths are provided for delivering electrolyte to and away from the plating chamber. Additionally, a vented electrolyte manifold is disposed in the electrolyte delivery path immediately upstream of the plating chamber, the vented electrolyte manifold comprising one or more electrolyte delivery openings that open to the plating chamber and one or more vents that open to a location other than the plating chamber.Type: GrantFiled: December 17, 2008Date of Patent: July 2, 2013Assignee: Novellus Systems, Inc.Inventors: Jingbin Feng, Zhian He, Robert Rash, Steven T. Mayer
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Patent number: 8475636Abstract: An apparatus for electroplating a layer of metal onto the surface of a wafer includes an ionically resistive ionically permeable element located in close proximity of the wafer and an auxiliary cathode located between the anode and the ionically resistive ionically permeable element. The ionically resistive ionically permeable element serves to modulate ionic current at the wafer surface. The auxiliary cathode is configured to shape the current distribution from the anode. The provided configuration effectively redistributes ionic current in the plating system allowing plating of uniform metal layers and mitigating the terminal effect.Type: GrantFiled: June 9, 2009Date of Patent: July 2, 2013Assignee: Novellus Systems, Inc.Inventors: Steven Mayer, Jingbin Feng, Zhian He, Jonathan Reid, Seshasayee Varadarajan
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Patent number: 8475644Abstract: An apparatus for electroplating a layer of metal onto the surface of a wafer includes an ionically resistive ionically permeable element located in close proximity of the wafer and an auxiliary cathode located between the anode and the ionically resistive ionically permeable element. The ionically resistive ionically permeable element serves to modulate ionic current at the wafer surface. The auxiliary cathode is configured to shape the current distribution from the anode. The provided configuration effectively redistributes ionic current in the plating system allowing plating of uniform metal layers and mitigating the terminal effect.Type: GrantFiled: October 26, 2009Date of Patent: July 2, 2013Assignee: Novellus Systems, Inc.Inventors: Steven Mayer, Jingbin Feng, Zhian He, Jonathan Reid, Seshasayee Varadarajan
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Publication number: 20130160946Abstract: An apparatus for purging a space in a processing chamber comprises a source of a purge gas; an inlet portion of a purge ring; an inlet baffle located in the inlet portion and fluidically connected to the source of purge gas; and an exhaust portion of the purge ring. The inlet portion and the exhaust portion define a ring hole space having a 360° periphery. The inlet baffle preferably surrounds not less than 180° of said periphery. The inlet baffle is operable to convey purge gas into the ring hole space. The exhaust portion is operable to convey purge gas and other matter out of the ring hole space. Cleaning of the purge ring and other structures in a processing chamber is conducted by flowing a cleaning gas through the inlet baffle. Some embodiments include a gas inlet plenum and an exhaust channel but not a purge ring.Type: ApplicationFiled: July 31, 2012Publication date: June 27, 2013Applicant: Novellus Systems, Inc.Inventors: Eugene Smargiassi, Stephen Yu-Hong Lau, George D. Kamian, Ming Xi
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Patent number: 8470191Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.Type: GrantFiled: August 6, 2007Date of Patent: June 25, 2013Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, Mark L. Rea, Richard S. Hill, Avishai Kepten, R. Marshall Stowell, Eric G. Webb
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Patent number: 8465991Abstract: A method for the ultraviolet (UV) treatment of carbon-containing low-k dielectric and associated apparatus enables process induced damage repair. The methods of the invention are particularly applicable in the context of damascene processing to recover lost low-k property of a dielectric damaged during processing, either pre-metallization, post-planarization, or both. UV treatments can include an exposure of the subject low-k dielectric to a constrained UV spectral profile and/or chemical silylating agent, or both.Type: GrantFiled: December 20, 2010Date of Patent: June 18, 2013Assignee: Novellus Systems, Inc.Inventors: Bhadri N. Varadarajan, Kevin M. McLaughlin, Bart van Schravendijk
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Patent number: 8454750Abstract: The present invention addresses provides improved methods of preparing a low-k dielectric material on a substrate. The methods involve multiple operation ultraviolet curing processes in which UV intensity, wafer substrate temperature and other conditions may be independently modulated in each operation. In certain embodiments, a film containing a structure former and a porogen is exposed to UV radiation in a first operation to facilitate removal of the porogen and create a porous dielectric film. In a second operation, the film is exposed to UV radiation to increase cross-linking within the porous film. In certain embodiments, the curing takes place in a multi-station UV chamber wherein UV intensity and substrate temperature may be independently controlled at each station.Type: GrantFiled: March 20, 2007Date of Patent: June 4, 2013Assignee: Novellus Systems, Inc.Inventors: Krishnan Shrinivasan, Michael Rivkin, Eugene Smargiassi, Mohamed Sabri
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Patent number: 8454294Abstract: Apparatuses and methods for cooling and transferring wafers from low pressure environment to high pressure environment are provided. An apparatus may include a cooling pedestal and a set of supports for holding the wafer above the cooling pedestal. The average gap between the wafer and the cooling pedestal may be no greater than about 0.010 inches. Venting gases may be used to increase the pressure inside the apparatus during the transfer. In certain embodiment, venting gases comprise nitrogen.Type: GrantFiled: September 7, 2011Date of Patent: June 4, 2013Assignee: Novellus Systems, Inc.Inventors: Christopher Gage, Charles E. Pomeroy, David Cohen, Nagarajan Kalyanasundaram
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Patent number: 8450210Abstract: Methods and apparatus are provided for processing semiconductor wafers sequentially. Sequential processes employ multi-station processing modules, where particular encompassing wafer processes are divided into sub-processes, each optimized for increasing wafer to wafer uniformity, result quality, and overall wafer throughput. In one example, a copper electroplating module includes separate stations for wetting, initiation, seed layer repair, fill, overburden, reclaim, and rinse.Type: GrantFiled: August 25, 2011Date of Patent: May 28, 2013Assignee: Novellus Systems, Inc.Inventors: Evan E. Patton, Theodore Cacouris, Eliot Broadbent, Steven T. Mayer
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Patent number: 8449731Abstract: Local plasma density, e.g., the plasma density in the vicinity of the substrate, is increased by providing an ion extractor configured to transfer ions and electrons from a first region of magnetically confined plasma (typically a region of higher density plasma) to a second region of plasma (typically a region of lower density plasma). The second region of plasma is preferably also magnetically shaped or confined and resides between the first region of plasma and the substrate. A positively biased conductive member positioned proximate the second region of plasma serves as an ion extractor. A positive bias of about 50-300 V is applied to the ion extractor causing electrons and subsequently ions to be transferred from the first region of plasma to the vicinity of the substrate, thereby forming higher density plasma. Provided methods and apparatus are used for deposition and resputtering.Type: GrantFiled: February 23, 2011Date of Patent: May 28, 2013Assignee: Novellus Systems, Inc.Inventors: Anshu A. Pradhan, Douglas B. Hayden, Ronald L. Kinder, Alexander Dulkin
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Patent number: 8444869Abstract: A method and apparatus for cleaning a wafer. The wafer is heated and moved to a processing station within the apparatus that has a platen either permanently in a platen down position or is transferable from a platen up position to the platen down position. The wafer is positioned over the platen so as not to contact the platen and provide a gap between the platen and wafer. The gap may be generated by positioning the platen in a platen down position. A plasma flows into the gap to enable the simultaneous removal of material from the wafer front side, backside and edges. The apparatus may include a single processing station having the gap residing therein, or the apparatus may include a plurality of processing stations, each capable of forming the gap therein for simultaneously removing additional material from the wafer front side, backside and edges.Type: GrantFiled: May 24, 2010Date of Patent: May 21, 2013Assignee: Novellus Systems, Inc.Inventors: Haruhiro Harry Goto, David Cheung
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Patent number: 8435895Abstract: Methods are provided for cleaning metal regions overlying semiconductor substrates. A method for removing material from a metal region comprises heating the metal region, forming a plasma from a gas comprising hydrogen and carbon dioxide, and exposing the metal region to the plasma.Type: GrantFiled: April 4, 2007Date of Patent: May 7, 2013Assignee: Novellus Systems, Inc.Inventors: David Chen, Haruhiro Harry Goto, Martina Martina, Frank Greer, Shamsuddin Alokozai
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Patent number: 8435608Abstract: Provided are plasma enhanced chemical vapor deposition methods of depositing smooth and conformal ashable hard mask films on substrates containing raised or recessed features. The methods involve using precursors having relatively high C:H ratios, such as acetylene (C:H ratio of 1), and plasmas having low ion energies and fluxes. According to various embodiments, the methods involve depositing smooth ashable hard mask films using high frequency radio frequency-generated plasmas with no low frequency component and/or relatively high pressures (e.g., 2-5 Torr). Also provided are methods of depositing ashable hard mask films having good selectivity and improved side wall coverage and roughness. The methods involve depositing a first ashable hard mask film on a substrate having a feature using a process optimized for selectivity and/or optical properties and then depositing a smoothing layer on the first ashable hard mask film using an HF-only process.Type: GrantFiled: June 27, 2008Date of Patent: May 7, 2013Assignee: Novellus Systems, Inc.Inventors: Pramod Subramonium, Zhiyuan Fang, Shawn Hancock, Mike Pierce, Jon Henri
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Patent number: 8435894Abstract: Methods and apparatuses for filling high aspect ratio features with tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a tungsten-containing material followed by selectively removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ration feature. In certain embodiments, the remaining layer is more passivated near the feature opening than inside the feature. The method may proceed with depositing an additional layer of the same or other material over the remaining layer. The deposition rate during this later deposition operation is slower near the feature opening than inside the features due to the differential passivation of the remaining layer. This deposition variation, in turn, may aid in preventing premature closing of the feature and facilitate filling of the feature in a substantially void free manner.Type: GrantFiled: January 17, 2012Date of Patent: May 7, 2013Assignee: Novellus Systems, Inc.Inventors: Anand Chandrashekar, Raashina Humayun, Michal Danek, Aaron R. Fellis, Sean Chang
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Patent number: 8430992Abstract: Protective self aligned buffer (PSAB) layers are layers of material that are selectively formed at the surface of metal layers in a partially fabricated semiconductor device. In a Damascene interconnect, PSAB layer typically resides at an interface between the metal layer and a dielectric diffusion barrier layer. PSAB layers promote improved adhesion between a metal layer and an adjacent dielectric diffusion barrier layer. Further, PSAB layers can protect metal surfaces from inadvertent oxidation during fabrication process. A PSAB layer may be formed entirely within the top portion of a metal layer, by, for example, chemically converting metal surface to a thin layer of metal silicide. Thickness of PSAB layers, and, consequently resistance of interconnects can be controlled by partially passivating metal surface prior to formation of PSAB layer. Such passivation can be accomplished by controllably treating metal surface with a nitrogen-containing compound to convert metal to metal nitride.Type: GrantFiled: April 20, 2010Date of Patent: April 30, 2013Assignee: Novellus Systems, Inc.Inventors: Kaushik Chattopadhyay, Bart van Schravendijk
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Patent number: 8431033Abstract: A physical vapor deposition (PVD) system and method includes a chamber including a target and a pedestal supporting a substrate. A target bias device supplies DC power to the target during etching of the substrate. The DC power is greater than or equal to 8 kW. A magnetic field generating device, including electromagnetic coils and/or permanent magnets, creates a magnetic field in a chamber of the PVD system during etching of the substrate. A radio frequency (RF) bias device supplies an RF bias to the pedestal during etching of the substrate. The RF bias is less than or equal to 120V at a predetermined frequency. A magnetic field produced in the target is at least 100 Gauss inside of the target.Type: GrantFiled: December 21, 2010Date of Patent: April 30, 2013Assignee: Novellus Systems, Inc.Inventors: Chunming Zhou, Liqi Wu, Karthik Colinjivadi, Emery Kuo, Huatan Qiu, KieJin Park
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Patent number: 8430620Abstract: Methods, systems and apparatuses for high throughput substrate transfer are provided. According to various embodiments, the methods and systems described use robots having dedicated end effectors for hot and cold wafers or other substrates). Throughput is increased by optimizing the transfer of both the hot and the cold wafers. Also described are wafer transfer apparatuses having end effectors configured for supporting either hot or cold wafers. In certain embodiments, dual arm robots having dedicated hot and cold wafer arms are provided. Also provided are methods of transferring substrates that to improve overall throughput. The methods involve transferring hot and cold substrates at different accelerations.Type: GrantFiled: March 24, 2008Date of Patent: April 30, 2013Assignee: Novellus Systems, Inc.Inventor: Rich Blank
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Patent number: 8426778Abstract: The present invention provides improved apparatus for ultraviolet (UV) cure of thin films. A central external reflector (CER) reflects UV light at different angles to compensate for non-uniformity of the deposited film on the substrate. The CER is positioned between the UV light source and the substrate and includes an actuator that can change the angle of reflection before and during UV cure.Type: GrantFiled: December 10, 2007Date of Patent: April 23, 2013Assignee: Novellus Systems, Inc.Inventor: Bryan Bolt