Abstract: A lithography reticle advantageously includes “proximity effect halos” around tight tolerance features. During reticle formation, the tight tolerance features and associated halos can be carefully written and inspected to ensure accuracy while the other portions of the reticle can be written/inspected less stringently for efficiency. A system for creating a reticle data file from an IC layout data file can include a processing module and a graphical display. The processing module can read the IC layout data file, identify critical features and define a halo region around each of the critical features. The graphical user interface can facilitate user input and control. The system can be coupled to a remote IC layout database through a LAN or a WAN.

Abstract: One embodiment of the invention provides a method that facilitates selectively varying how much of a layout of an integrated circuit is defined by phase shifters during an optical lithography process used in manufacturing the integrated circuit. During operation, the method receives a specification of the layout of the integrated circuit. The method then assigns features within the layout to zones associated with different phase shifting priorities. Next, the method generates a phase shifter placement by placing phase shifters comprised of phase shifting geometries onto a phase shifting mask to define the features within the layout, wherein the phase shifter placement is subject to coloring constraints. Note that in general there is no restriction on the order of zone placement. During this placement process, if coloring constraints cannot be satisfied, the method resolves conflicts and/or removes features from being phase-shifted based upon phase shifting priorities of the zones.

Abstract: A full phase shifting mask (FPSM) can define substantially all of the features of an integrated circuit using pairs of shifters having opposite phase. In particular, cutting patterns for working with the polysilicon, or gate, layers and active layers of static random access memory (SRAM) cells are considered. To resolve phase conflicts between shifters, one or more cutting patterns can be selected. These cutting patterns include cuts on contact landing pads. This cut simplifies the FPSM layout while ensuring greater critical dimension control of the more important features and reducing mask misalignment sensitivity.

Abstract: Phase shifting allows generating very narrow features in a printed features layer. Thus, forming a fabrication layout for a physical design layout having critical features typically includes providing a layout for shifters. Specifically, pairs of shifters can be placed to define critical features, wherein the pairs of shifters conform to predetermined design rules. After placement, phase information for the shifters associated with the set of critical features can be assigned. Complex designs can lead to phase-shift conflicts among shifters in the fabrication layout. An irresolvable conflict can be passed to the design process earlier than in a conventional processes, thereby saving valuable time in the fabrication process for printed circuits.

Abstract: One embodiment of the invention provides a system for generating trim to be used in conjunction with phase shifters during an optical lithography process for manufacturing an integrated circuit. The system operates by identifying a feature within the integrated circuit to be created by using a phase shifter to produce a region of destructive light interference on a photoresist layer. Next, the system generates the phase shifter for a first mask, while ensuring that design rules are satisfied in defining dimensions for the phase shifter. After the phase shifter is generated, the system generates trim within a second mask, that is used in conjunction with the first mask, by deriving the trim from the previously-defined dimensions of the phase shifter while ensuring that the design rules are satisfied. Note that the design rules can be satisfied by cutting and/or patching portions of the phase shifter and associated trim.

Abstract: Mask simulation tools are typically extremely complicated to learn and to use effectively. Therefore, providing access to a mask simulation tool over a wide area network (WAN) to multiple on-line users can be very cost effective. Specifically, in a network-based simulation server, multiple users can view the same mask image, simulations, and analysis results and provide real-time comments to each other as simulation and analysis are performed, thereby encouraging invaluable problem-solving dialogue among users. The user interface for this mask simulation tool can advantageously facilitate this dialogue. For example, the user interface can include an enter box for a user to enter a message and a talk box for capturing any message sent by any user of the simulation tool using the enter box.

Abstract: A method of optimizing a wafer fabrication process for a given mask is provided. The method includes capturing an image of a mask and simulating a wafer image of the mask. A mask map of information can then be generated based on the simulated wafer image. The resulting mask map can be provided to any downstream wafer fabrication process when such process involves the mask. One or more one input parameters to the downstream wafer fabrication process can be changed based on the mask map, thereby optimizing the process for the given mask.

Abstract: One embodiment of the invention provides a system that facilitates minimum spacing and/or width control during an optical proximity correction operation for a layout of a mask used in manufacturing an integrated circuit. During operation, the system considers a target edge of a first feature on the mask and then identifies a set of interacting edges in proximity to the target edge. Next, the system performs the optical proximity correction operation, wherein performing the optical proximity correction operation involves applying a first edge bias to the target edge to compensate for optical effects in a resulting image of the target edge. While applying the first edge bias to the target edge, the system allocates an available bias between the first edge bias for the target edge and a second edge bias for at least one edge in the set of interacting edges.

Abstract: A method and system of determining a sensitivity of an edge of a feature to mask error can be advantageously provided using information from multiple simulations. Input data as well as revised data regarding the edge can be used, wherein the revised data includes a first mask error. The input data can be simulated to generate first deviation information, whereas the revised data can be simulated to generate second deviation information accounting for the first mask error. The sensitivity of the edge to mask error can be generated using the first deviation information, the second deviation information, and the first mask error. Specifically, generating the sensitivity can include subtracting the first deviation information from the second deviation and dividing the difference by the first mask error.

Abstract: A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.

Abstract: Phase shifting generates features in a printed features layer, such as a printed circuit, that are narrower than the features on a fabrication layout, such as a mask, projected onto the printed features layer using the same optical system without phase shifting. Techniques for forming a fabrication layout for a physical design layout having critical features employing phase shifting include techniques for providing a layout for shifters. The techniques include establishing placement of multiple pairs of shifters for a set of critical features. A critical feature employs phase shifting. The set of critical features constitutes a subset of all critical features in a layout. After establishing placement of the pairs of shifters, phase information for the shifters associated with the set of critical features is assigned. This and related techniques expedite resolving phase-shift conflicts in fabrication layouts for phase-shifted features.

Abstract: A method of generating simulation reports regarding an integrated circuit layout is provided. The method can include providing a plurality of control points associated with the integrated circuit layout. A single simulation of the plurality of control points can be performed. Detailed information from the single simulation can be stored in a database. Desired information can then be extracted from the database to generate the simulation reports.

Abstract: One embodiment of the present invention provides a system that controls rippling caused by optical proximity correction during an optical lithography process for manufacturing an integrated circuit. During operation, the system selects an evaluation point for a given segment, wherein the given segment is located on an edge in the layout of the integrated circuit. The system also selects a supplemental evaluation point for the given segment. Next, the system computes a deviation from a target location for the given segment at the evaluation point. The system also computes a supplemental deviation at the supplemental evaluation point. Next, the system adjusts a bias for the given segment, if necessary, based upon the deviation at the evaluation point. The system also calculates a ripple for the given segment based upon the deviation at the evaluation point and the supplemental deviation at the supplemental evaluation point.

Abstract: Techniques for fabricating a device include forming a fabrication layout, such as a mask layout, for a physical design layer, such as a design for an integrated circuit, and identifying evaluation points on an edge of a polygon corresponding to the design layer for correcting proximity effects. Techniques include correcting for proximity effects associated with an edge in a first fabrication layout by determining whether any portion of the edge corresponds to a target edge in a design layer. The first fabrication layout corresponds to the design layer that indicates target edges for a printed features layer. If any portion of the edge corresponds to the target edge, then it is determined whether to establish an evaluation point on the edge. Then it is determined how to correct the edge for proximity effects based on the evaluation point. In case it is determined that no portion of the edge corresponds to the target edge, then no evaluation point is selected on the edge.

Abstract: A mask defect printability simulation server provides simulations, one-dimensional analysis, and reports to multiple clients over a wide area network, such as the Internet. This network-based simulation server allows a client to leverage a core of highly-trained engineers. Additionally, the network-based simulation server can be easily supported since only a single source for the tools associated with the simulation server is necessary for multiple clients. A client can access the simulation server using a standard personal computer having a browser, thereby eliminating the need for client to maintain an expensive database for the server. Finally, in the network-based simulation server, multiple users can view the same mask defect image and provide real-time comments to each other as simulation and analysis are performed on the defect image, thereby encouraging problem solving and decision-making dialogue among the users.

Abstract: A reference image is generated from a subject image of at least a portion of a photolithography mask to enable a photolithography mask inspection and analysis system that otherwise cannot generate a reference image from a reference die or digitized design data, for example, to perform a mask analysis using the reference image. A mask inspection and analysis system may then be enhanced to perform one or more additional mask analyses to analyze the mask. The reference image is generated by identifying a defect or contaminant of the mask in the subject image and modifying the subject image to remove the defect or contaminant from the mask to generate the reference image. For one embodiment, a system using a STARlight inspection tool that captures transmitted and reflected images of a portion of a mask may then be enhanced to perform one or more mask analyses that use a reference image.

Abstract: One embodiment of the invention provides a system for reducing incidental exposure caused by phase shifting during fabrication of a semiconductor chip. The system operates by identifying a problem area of likely incidental exposure in close proximity to an existing phase shifter on a phase shifting mask, wherein the problem area includes a polysilicon line passing through a field region of the semiconductor chip. The system places an additional phase shifter into the problem area on the phase shifting mask so that a regulator within the additional phase shifter protects the polysilicon line passing through the field region. This additional phase shifter has a wider regulator than the existing phase shifter, wherein the existing phase shifter is used to expose a polysilicon line in a gate region of the semiconductor chip.

Abstract: One embodiment of the invention provides a method and a system for using phase shifter cutbacks to resolve conflicts between phase shifters during creation of a mask to be used in an optical lithography process for manufacturing an integrated circuit. The system works by locating a plurality of phase shifters, including a first phase shifter and a second phase shifter, on a phase shifting mask, and then identifying a conflict area wherein a conflict is likely to occur between the first phase shifter and the second phase shifter on the phase shifting mask. The system resolves this conflict by cutting back one or both of the first phase shifter and the second phase shifter, so that the first phase shifter and the second phase shifter do not interfere with each other in the conflict area.

Abstract: A semiconductor layout testing and correction system is disclosed. The system combines both rule-based optical proximity correction and model-based optical proximity correction in order to test and correct semiconductor layouts. In a first embodiment, a semiconductor layout is first processed by a rule-based optical proximity correction system and then subsequently processed by a model-based optical proximity correction system. In another embodiment, the system first processes a semiconductor layout with a rule-based optical proximity correction system and then selectively processes difficult features using a model-based optical proximity correction system. In yet another embodiment, the system selectively processes the various features of a semiconductor layout using a rule-based optical proximity correction system or a model-based optical proximity correction system.

Abstract: A two mask process for small dimension features on an integrated circuit improves manufacturability and design tolerance. The first mask is an opaque-field phase shift mask and the second mask is a single phase structure mask. A phase shift window is aligned with the opaque field using a phase shift overlap area on the opaque field. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask.