Abstract: An anti-virus chip includes a first connection terminal, a second connection terminal, a detection unit and a processing unit. The first connection terminal and the second connection terminal are respectively coupled to a connection port and a system circuit of an electronic device. The detection unit detects whether the connection port is connected to an external device via the first connection terminal. When the detection unit detects that the connection port is connected to the external device, the processing unit performs a virus-scan program on the external device to determine whether a virus exists in the external device. When determining that a virus does not exist in the external device, the processing unit establishes a first transmission path between the first connection terminal and the second connection terminal. When determining that a virus exists in the external device, the processing unit does not establish the first transmission path.

Abstract: A semiconductor light-emitting element includes: a semiconductor stack including an n-type layer and a p-type layer and having at least one n exposure portion being a recess where the n-type layer is exposed; a p wiring electrode layer on the p-type layer; an insulating layer (i) continuously covering inner lateral surfaces of at least one n exposure portion and part of a top surface of the p wiring electrode layer and (ii) having an opening portion that exposes the n-type layer; an n wiring electrode layer disposed above the p-type layer and the p wiring electrode layer and in contact with the n-type layer in the opening portion; and at least one first n connecting member connected to the n wiring electrode layer in at least one first n terminal region. The n wiring electrode layer and the p-type layer are disposed below at least one first n terminal region.

Abstract: A class-D driver circuit includes a feedback loop including an input integrator stage, a switched modulator, and an output driver stage. A feedback resistor connects an output terminal of the output driver stage with an input node of the input integrator stage to provide a feedback current. The class-D driver circuit also includes a compensation circuit configured to provide a compensation current to an output node of the input integrator stage to relieve a slew rate limitation of the feedback loop, the compensation current having a magnitude based on the magnitude of the feedback current.

Abstract: A processing circuit including a first oscillation circuit, a second oscillation circuit, a counting circuit, and a control circuit is provided. The first oscillation circuit receives an input voltage and generates a first clock signal according to the input voltage. The second oscillation circuit receives an output voltage and generates a second clock signal according to the output voltage. The counting circuit receives the output voltage. The counting circuit adjusts a first counter value according to the first clock signal and adjusts a second counter value according to the second clock signal. The control circuit receives the output voltage and determines whether the input voltage is experiencing an attack according to the first counter value and the second counter value. The first oscillation circuit operates in an un-protected power domain. The second oscillation circuit, the counting circuit, and the control circuit operate in a protected power domain.

Abstract: A nitride-based semiconductor light-emitting element includes: a substrate that is an example of a n-type nitride-based semiconductor including a group IV n-type impurity; and an n-side electrode in contact with the substrate. The substrate includes: a surface layer region in contact with the n-side electrode and including a halogen element; and an internal region located across the surface layer region from the n-side electrode. A peak concentration of the group IV n-type impurity in the surface layer region is at least 1.0×1021 cm?3. A peak concentration of the halogen element in the surface layer region is at least 10% of the peak concentration of the group IV n-type impurity in the surface layer region. A concentration of the group IV n-type impurity in the internal region is lower than a concentration of the group IV n-type impurity in the surface layer region.

Abstract: A data retention circuit is provided in the invention. The data retention circuit includes a master latch circuit, a slave latch circuit, and a control circuit. The control circuit is coupled to the master latch circuit and the slave latch circuit and receives a clock signal from a clock circuit and a power management signal from a power management unit (PMU). In a normal operation mode, the control circuit transmits the clock signal to the master latch circuit and the slave latch circuit. In sleep mode, power to the master latch circuit is switched off and the control circuit transmits the power management signal to the slave latch circuit.

Abstract: A signal generation circuit including a first control circuit, a second control circuit, an arbiter circuit, and a digital-to-analog converter (DAC) circuit is provided. The first control circuit stores a first string of data. The first control circuit enables a first trigger signal in response to a first event occurring. The second control circuit stores a second string of data. The second control circuit enables a second trigger signal in response to a second event occurring. The arbiter circuit reads the first or second control circuit according to the order of priority to use the first string of data or the second string of data as a digital input in response to the first and second trigger signals being enabled. The DAC circuit converts the digital input to generate an analog output.

Abstract: A method for protecting data in an external memory based on an isolated execution environment is provided. The method is used in a processor in the isolated execution environment of a system-on-a-chip. The method includes: accessing an output command of a main system processor in a main system of the system-on-a-chip; reading first data from a shared memory in the main system according to the output command; encrypting the first data with a private key and generating encrypted first data; and outputting the encrypted first data to the external memory.

Abstract: A semiconductor device includes a substrate. The semiconductor device also includes a semiconductor layer disposed in the substrate. The semiconductor device further includes a first dielectric layer disposed on the semiconductor layer. The semiconductor device includes a second dielectric layer disposed on the first dielectric layer. The semiconductor device also includes a pair of thermopile segments disposed on the second dielectric layer. The first dielectric layer and the second dielectric layer form a chamber.

Abstract: A battery monitoring device includes: a pair of terminals for measuring voltage or current of a battery, and to which a filter unit including a capacitive element is connected; an AD converter that measures a waveform of voltage between the terminals during charging or discharging of the capacitive element; and a time constant calculation unit that calculates a time constant of the filter unit based on the waveform measured. The AD converter is, for example, a first AD converter or a second AD converter. The filter unit is, for example, a first filter unit or a second filter unit.

Abstract: A puncture forming method is a method of forming punctures in a sample by irradiating a surface of the sample with a light beam. The puncture forming method includes: forming a first puncture by irradiating a first position on the surface of the sample with a first pulse of the light beam; and after the forming of the first puncture, forming a second puncture which at least partially overlaps the first puncture by irradiating, with a second pulse of the light beam, a second position on the surface of the sample positioned away from the first position in a first direction. The second puncture has a tip which is positioned inside the sample and which is bent in a direction opposite to the first direction.

Abstract: A heating circuit is provided. The heating circuit is disposed in a chip which has a normal operation temperature range. The heating circuit includes a comparison circuit and a thermal-energy generation circuit. The comparison circuit compares a temperature voltage with a first threshold voltage. The temperature voltage represents a temperature of the chip. The thermal-energy generation circuit is controlled by the comparison circuit. When the temperature voltage is less than the first threshold voltage, the comparison circuit enables the thermal-energy generation circuit to generate thermal energy to raise the temperature of the chip.

Abstract: A comparator testing circuit and a testing method are provided. The comparator testing circuit includes a switching circuit, a comparator, and a determination circuit. The switching circuit receives a first signal, a second signal, and a switching signal, and outputs one of the first signal and the second signal as a first input signal and the other of the first signal and the second signal as a second input signal according to the switching signal. The comparator compares the first input signal with the second input signal to generate an output signal. The determination circuit determines whether the comparator is abnormal based on the switching signal and the output signal to generate an exception flag.

Abstract: A semiconductor device according to an aspect of the present disclosure includes: a plurality of line layers; a first line; and a second line that is not connected to the first line and is redundantly provided to transfer a signal having a level same as a level of a signal transferred through the first line. The first line and the second line are included in different layers out of the plurality of line layers, and a distance between the first line and the second line is longer than an interlayer distance between line layers next to each other out of the plurality of line layers.

Abstract: An electronic device includes a first memory controller, a second memory controller, and a memory access controller. The first memory controller stores setting information of a predetermined memory, wherein the predetermined memory is defined as an execute-only-memory. The second memory controller provides and sets an enabling register according to the setting information of the predetermined memory, and generates an enabling signal. The memory access controller accesses the first memory controller and the second memory controller to move the data of the predetermined memory to a predetermined memory space corresponding to the enabling register according to the enabling signal and the setting information of the predetermined memory.

Abstract: A solid-state imaging device includes: a photoelectric conversion element that is disposed on a semiconductor substrate and generates signal charges by photoelectric conversion; a first diffusion layer that holds signal charges transferred from the photoelectric conversion element; a capacitive element that holds signal charges overflowing from the photoelectric conversion element; an amplifier transistor that outputs a signal according to the signal charges in the first diffusion layer; a first contact that is connected to the first diffusion layer; a second contact that is connected to a gate of the amplifier transistor; and a first wire that connects the first contact and the second contact. A shortest distance between the semiconductor substrate and the first wire is less than a shortest distance between the semiconductor substrate and the capacitive element.

Abstract: A memory device includes a main memory, a first sub-memory and a controller. When the first sub-memory is erased, the first sub-memory generates a first erase completion signal. The controller receives an erase signal to erase the main memory. The controller performs an erase operation on the main memory according to the erase signal and the first erase completion signal.

Abstract: A radio-frequency power amplifier device includes: a carrier amplifier semiconductor device and a peak amplifier semiconductor device on a multilayer submount substrate; a bias power supply semiconductor device; second radio-frequency signal wiring that transmits a radio-frequency signal to the carrier amplifier semiconductor device and the peak amplifier semiconductor device; and carrier-amplifier bias power supply wiring that is wired in a third wiring layer and supplies a bias power supply voltage. The second radio-frequency signal wiring and the carrier-amplifier bias power supply wiring intersect in a plan view. The radio-frequency power amplifier device includes: a shield pattern that is located in a second wiring layer between a first wiring layer and the third wiring layer; and one or more connection vias disposed in an extension direction of the carrier-amplifier bias power supply wiring. The one or more connection vias are connected to the shield pattern.

Abstract: A system includes a memory and a processor. The memory is configured to store a machine learning (ML) model. The processor is configured to (i) obtain a set of training audio signals that are labeled with respective levels of distortion, (ii) convert the training audio signals into respective images, (iii) train the ML model to estimate the levels of the distortion based on the images, (iv) receive an input audio signal, (v) convert the input audio signal into an image, and (vi) estimate a level of the distortion in the input audio signal, by applying the trained ML model to the image.

Abstract: A memory device and an operating method thereof are provided. The memory device includes a memory controller, an address transforming circuit, and a memory array. The memory controller generates a programming address among multiple candidate programming addresses according to an application. The address transforming circuit stores multiple physical address data and multiple mask data. The physical address data respectively correspond to the candidate programming addresses. The address transforming circuit executes a first logical calculation according to the programming address, the physical address data, and the mask data to generate a physical address. The memory controller executes an access operation on the memory array according to the physical address.