Patents Assigned to NVidia
  • Patent number: 11893468
    Abstract: Apparatuses, systems, and techniques to identify a goal of a demonstration. In at least one embodiment, video data of a demonstration is analyzed to identify a goal. Object trajectories identified in the video data are analyzed with respect to a task predicate satisfied by a respective object trajectory, and with respect to motion predicate. Analysis of the trajectory with respect to the motion predicate is used to assess intentionality of a trajectory with respect to the goal.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: February 6, 2024
    Assignee: NVIDIA Corporation
    Inventors: Yu-Wei Chao, De-An Huang, Christopher Jason Paxton, Animesh Garg, Dieter Fox
  • Patent number: 11893653
    Abstract: The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one embodiment, the presented new approach or solution uses Operating System (OS) allocation on the central processing unit (CPU) combined with graphics processing unit (GPU) driver mappings to provide a unified virtual address (VA) across both GPU and CPU. The new approach helps ensure that a GPU VA pointer does not collide with a CPU pointer provided by OS CPU allocation (e.g., like one returned by “malloc” C runtime API, etc.).
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: February 6, 2024
    Assignee: NVIDIA Corporation
    Inventors: Amit Rao, Ashish Srivastava, Yogesh Kini
  • Patent number: 11892898
    Abstract: Configurations for data center component monitoring are disclosed. In at least one embodiment, movement of a server component is determined based on sensor data and the movement is used to diagnose a root cause for a server component failure.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: February 6, 2024
    Assignee: Nvidia Corporation
    Inventors: William Andrew Mecham, Ryan Albright, Benjamin Goska, William Ryan Weese, Aaron Richard Carkin, Michael Thompson
  • Patent number: 11893423
    Abstract: A parallel processing unit (PPU) can be divided into partitions. Each partition is configured to operate similarly to how the entire PPU operates. A given partition includes a subset of the computational and memory resources associated with the entire PPU. Software that executes on a CPU partitions the PPU for an admin user. A guest user is assigned to a partition and can perform processing tasks within that partition in isolation from any other guest users assigned to any other partitions. Because the PPU can be divided into isolated partitions, multiple CPU processes can efficiently utilize PPU resources.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 6, 2024
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Gregory Scott Palmer, Jonathon Stuart Ramsey Evans, Shailendra Singh, Samuel H. Duncan, Wishwesh Anil Gandhi, Lacky V. Shah, Sonata Gale Wen, Feiqi Su, James Leroy Deming, Alan Menezes, Pranav Vaidya, Praveen Joginipally, Timothy John Purcell, Manas Mandal
  • Patent number: 11891036
    Abstract: In various examples, activation criteria and/or braking profiles corresponding to automatic emergency braking (AEB) systems and/or collision mitigation warning (CMW) systems may be determined using sensor data representative of an environment to a front, side, and/or rear of a vehicle. For example, activation criteria for triggering an AEB system and/or CMW system may be adjusted by leveraging the availability of additional information with regards to the surrounding environment of a vehicle—such as the presence of a trailing vehicle. In addition, the braking profile for the AEB activation may be adjusted based on information about the presence of and/or location of vehicles to the front, rear, and/or side of the vehicle. By adjusting the activation criteria and/or braking profiles of an AEB system, the potential for collisions with dynamic objects in the environment is reduced and the overall safety of the vehicle and its passengers is increased.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: February 6, 2024
    Assignee: NVIDIA Corporation
    Inventors: Mark Henry Costin, Jonathan Sweedler
  • Patent number: 11892629
    Abstract: Virtual reality (VR) displays are computer displays that present images or video in a manner that simulates a real experience for the viewer. In many cases, VR displays are implemented as head-mounted displays (HMDs) which provide a display in the line of sight of the user. Because current HMDs are composed of a display panel and magnifying lens with a gap therebetween, proper functioning of the HMDs limits their design to a box-like form factor, thereby negatively impacting both comfort and aesthetics. The present disclosure provides a different configuration for a VR display which allows for improved comfort and aesthetics, including specifically at least one coherent light source, at least one pupil replicating waveguide coupled to the at least one coherent light source to receive light therefrom, and at least one spatial light modulator coupled to the at least one pupil replicating waveguide to modulate the light.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: February 6, 2024
    Assignee: NVIDIA CORPORATION
    Inventors: Jonghyun Kim, Ward Lopes, David Patrick Luebke, Manu Gopakumar
  • Patent number: 11895809
    Abstract: Systems and methods for cooling a datacenter are disclosed. In at least one embodiment, a sensor string is associated with a first fluid line having a first flow controller and with a second fluid line having a second flow controller, so that sections of such a sensor string are enabled to maintain electrical connectivity there through by a mechanical coupling of a first flow controller and a second flow controller.
    Type: Grant
    Filed: May 12, 2021
    Date of Patent: February 6, 2024
    Assignee: Nvidia Corporation
    Inventor: Ali Heydari
  • Patent number: 11892946
    Abstract: Apparatuses, systems, and techniques to allocate portions of a virtual address space to allow virtual machines to share data. In at least one embodiment, at least a portion of a virtual memory address space is made accessible to multiple virtual machines and is mapped to memory addresses of different physical devices using, at least in part, a cache-coherent protocol.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: February 6, 2024
    Assignee: NVIDIA Corporation
    Inventor: Shirish Bahirat
  • Patent number: 11886634
    Abstract: In various examples, systems and methods are disclosed that provide highly accurate gaze predictions that are specific to a particular user by generating and applying, in deployment, personalized calibration functions to outputs and/or layers of a machine learning model. The calibration functions corresponding to a specific user may operate on outputs (e.g., gaze predictions from a machine learning model) to provide updated values and gaze predictions. The calibration functions may also be applied one or more last layers of the machine learning model to operate on features identified by the model and provide values that are more accurate. The calibration functions may be generated using explicit calibration methods by instructing users to gaze at a number of identified ground truth locations within the interior of the vehicle. Once generated, the calibration functions may be modified or refined through implicit gaze calibration points and/or regions based on gaze saliency maps.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: January 30, 2024
    Assignee: NVIDIA Corporation
    Inventors: Nuri Murat Arar, Sujay Yadawadkar, Hairong Jiang, Nishant Puri, Niranjan Avadhanam
  • Patent number: 11889122
    Abstract: A technique for streaming and a client device that uses the technique are disclosed herein. The disclosed technique determines context complexity of streamed data and determines whether to discard or select the streamed data for a future reference frame based on the context complexity of the streamed data. The streamed data is discarded if the content complexity is higher than a content complexity threshold, and the streamed data is selected if the content complexity is not higher than a content complexity threshold. This is based on the realization that error propagation in the case of a less complex video sequence is not very bothersome to the end user experience whereas corruption will be very severe in cases of highly complex sequences.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: January 30, 2024
    Assignee: NVIDIA Corporation
    Inventors: Thrinadh Kottana, Vinayak Pore, Chirayu Garg, Soumen Kumar Dey
  • Patent number: 11884294
    Abstract: In various examples, sensor data may be collected using one or more sensors of an ego-vehicle to generate a representation of an environment surrounding the ego-vehicle. The representation may include lanes of the roadway and object locations within the lanes. The representation of the environment may be provided as input to a longitudinal speed profile identifier, which may project a plurality of longitudinal speed profile candidates onto a target lane. Each of the plurality of longitudinal speed profiles candidates may be evaluated one or more times based on one or more sets of criteria. Using scores from the evaluation, a target gap and a particular longitudinal speed profile from the longitudinal speed profile candidates may be selected. Once the longitudinal speed profile for a target gap has been determined, the system may execute a lane change maneuver according to the longitudinal speed profile.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: January 30, 2024
    Assignee: NVIDIA Corporation
    Inventors: Zhenyi Zhang, Yizhou Wang, David Nister, Neda Cvijetic
  • Patent number: 11886885
    Abstract: One embodiment of the present invention sets forth a data pipeline, which includes a first mousetrap element and a second mousetrap element in a first pipeline stage. Each mousetrap element includes a request latch that, when enabled, allows a request signal to pass from the first pipeline stage to a second pipeline stage following the first pipeline stage in the data pipeline. Each mousetrap element also includes a data latch that, when enabled, allows a data element to pass from the first pipeline stage to the second pipeline stage. Each mousetrap element further includes a latch controller that enables and disables the request and data latches based on a phase signal that alternates between a first value that configures the first mousetrap element to transmit data to the second pipeline stage and a second value that configures the second mousetrap element to transmit data to the second pipeline stage.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: January 30, 2024
    Assignee: NVIDIA Corporation
    Inventor: Benjamin Andrew Keller
  • Patent number: 11886980
    Abstract: Neural networks, in many cases, include convolution layers that are configured to perform many convolution operations that require multiplication and addition operations. Compared with performing multiplication on integer, fixed-point, or floating-point format values, performing multiplication on logarithmic format values is straightforward and energy efficient as the exponents are simply added. However, performing addition on logarithmic format values is more complex. Conventionally, addition is performed by converting the logarithmic format values to integers, computing the sum, and then converting the sum back into the logarithmic format. Instead, logarithmic format values may be added by decomposing the exponents into separate quotient and remainder components, sorting the quotient components based on the remainder components, summing the sorted quotient components to produce partial sums, and multiplying the partial sums by the remainder components to produce a sum.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: January 30, 2024
    Assignee: NVIDIA Corporation
    Inventors: William James Dally, Rangharajan Venkatesan, Brucek Kurdo Khailany
  • Patent number: 11886744
    Abstract: A method, computer program product, apparatus, and system are provided. Some embodiments may include transmitting a request to make one or more writes associated with an identification tag. The request may include the identification tag, the one or more writes, a first instruction to make the one or more writes to one of a plurality of persistence levels of a memory, and a second instruction to respond with at least one first indication that the one or more writes associated with the identification tag have been written to at least one of the one of the plurality of persistence levels of the memory. Some embodiments may include receiving the at least one first indication that the one or more writes associated with the identification tag have been written to at least one of the one of the plurality of persistence levels of the memory.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: January 30, 2024
    Assignee: NVIDIA CORPORATION
    Inventor: Stephen David Glaser
  • Patent number: 11887245
    Abstract: One embodiment of a method for rendering one or more graphics images includes tracing one or more rays through a graphics scene; computing one or more surface normals associated with intersections of the one or more rays with one or more surfaces, where computing each surface normal includes: computing a plurality of intermediate surface normals associated with a plurality of adjacent voxels of a grid, and interpolating the plurality of intermediate surface normals; and rendering one or more graphics images based on the one or more surface normals.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: January 30, 2024
    Assignee: NVIDIA Corporation
    Inventors: Herman Hansson Soederlund, Alex Evans, Tomas Akenine-Moller
  • Patent number: 11886262
    Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: January 30, 2024
    Assignee: NVIDIA Corporation
    Inventors: Sau Yan Keith Li, Thomas E. Dewey, Arthur Chen, Simon Lai, Amit Pabalkar, Santosh Nayak
  • Patent number: 11885907
    Abstract: In various examples, a deep neural network(s) (e.g., a convolutional neural network) may be trained to detect moving and stationary obstacles from RADAR data of a three dimensional (3D) space, in both highway and urban scenarios. RADAR detections may be accumulated, ego-motion-compensated, orthographically projected, and fed into a neural network(s). The neural network(s) may include a common trunk with a feature extractor and several heads that predict different outputs such as a class confidence head that predicts a confidence map and an instance regression head that predicts object instance data for detected objects. The outputs may be decoded, filtered, and/or clustered to form bounding shapes identifying the location, size, and/or orientation of detected object instances. The detected object instances may be provided to an autonomous vehicle drive stack to enable safe planning and control of the autonomous vehicle.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: January 30, 2024
    Assignee: NVIDIA Corporation
    Inventors: Alexander Popov, Nikolai Smolyanskiy, Ryan Oldja, Shane Murray, Tilman Wekel, David Nister, Joachim Pehserl, Ruchi Bhargava, Sangmin Oh
  • Publication number: 20240030918
    Abstract: Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, and control drivers powered by moving supply voltages generated by the storage cell, wherein the control drivers coupled to drive gates of common-source configured devices coupled to storage nodes of the storage cell.
    Type: Application
    Filed: September 14, 2022
    Publication date: January 25, 2024
    Applicant: NVIDIA Corp.
    Inventors: Walker Joseph Turner, John Poulton, Sanquan Song
  • Publication number: 20240030916
    Abstract: A level-shifting circuits utilizing storage cells for shifting signals low-to-high or high-to-low include control drivers with moving supply voltages. The moving supply voltages may power positive or negative supply terminals of the control drivers. The control drivers drive gates of common-source configured devices coupled to storage nodes of the storage cell.
    Type: Application
    Filed: September 14, 2022
    Publication date: January 25, 2024
    Applicant: NVIDIA Corp.
    Inventors: Walker Joseph Turner, John Poulton, Sanquan Song
  • Publication number: 20240030917
    Abstract: Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell and control drivers powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, wherein the control drivers are coupled to drive common-source configured devices coupled to storage nodes of the storage cell.
    Type: Application
    Filed: September 14, 2022
    Publication date: January 25, 2024
    Applicant: NVIDIA Corp.
    Inventors: Walker Joseph Turner, John Poulton, Sanquan Song