Patents Assigned to NVidia
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Patent number: 12177961Abstract: According to various embodiments, a processing subsystem includes: a processor mounted on a first printed circuit board that is oriented parallel to a first plane; a heat sink thermally coupled to the processor; a second printed circuit board that is communicatively coupled to the first printed circuit board and oriented parallel to a second plane, wherein the second plane is not parallel with the first plane; and at least one cooling fan that is positioned to direct a cooling fluid through the heat sink in a direction parallel to the first plane.Type: GrantFiled: October 21, 2022Date of Patent: December 24, 2024Assignee: NVIDIA CORPORATIONInventors: Xiang Sun, Andrew Bell, Gabriele Gorla, Boris Landwehr, Darryl Moore
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Patent number: 12175703Abstract: Apparatuses, systems, and techniques to determine a pose and relative dimensions of an object from an image. In at least one embodiment, a pose and relative dimensions of an object are determined from an image based at least in part on, for example, features of the image.Type: GrantFiled: September 9, 2021Date of Patent: December 24, 2024Assignee: NVIDIA CorporationInventors: Stanley Thomas Birchfield, Jonathan Tremblay, Yunzhi Lin, Stephen Walter Tyree
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Patent number: 12174602Abstract: A thermal load system for testing a datacenter liquid cooling system is disclosed. The system includes a server box having at least one thermal feature associated with at least one cooling feature and at least one flow controller, where the at least one thermal feature and the at least one flow controller are adjustable to cause cooling stress on the datacenter liquid cooling system.Type: GrantFiled: August 4, 2020Date of Patent: December 24, 2024Assignee: NVIDIA CorporationInventor: Ali Heydari
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Patent number: 12174034Abstract: A computer-implemented method may comprise: receiving sensor data from a sensor of an autonomous vehicle; determining a presence of a lane closure object located on a lane element; determining a change of the lane closure object, selected from the presence of the lane closure object or absence of the lane closure object on the lane element; generating a change candidate based on the change in the lane closure object; obtaining a plurality of the change candidates during a time period or the autonomous vehicle being on a preceding lane element on the route; analyzing the plurality of change candidates for the change being the presence of the lane closure object or the absence of the lane closure object on the lane element; generating a final change candidate based on the change; and providing the final change candidate for updating a high definition map of the route having the lane element.Type: GrantFiled: October 10, 2023Date of Patent: December 24, 2024Assignee: NVIDIA CORPORATIONInventors: Ronghua Zhang, Marlene Wan, Yinghui Yao
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Publication number: 20240420748Abstract: Negative bit line voltage assist mechanisms for multi-bank machine memories utilizing multiple local IO drivers include a shared boost capacitor configured to generate a negative bit line voltage assist for write operations by local IO drivers, where the boost capacitor is configured to selectively couple to one of the local IO drivers during the write operation.Type: ApplicationFiled: June 16, 2023Publication date: December 19, 2024Applicant: NVIDIA Corp.Inventors: Cagri Erbagci, Burak Erbagci, Lalit Gupta, Jesse San-Jey Wang
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Patent number: 12169677Abstract: A genetic algorithm is utilized to generate routing candidates to which a reinforcement learning model is applied to correct the design rule constraint violations incrementally. A design rule checker provides feedback on the violations to the reinforcement learning model and the model learns how to fix the violations. A layout device placer based upon a simulated annealing method may also be utilized.Type: GrantFiled: April 14, 2021Date of Patent: December 17, 2024Assignee: NVIDIA Corp.Inventors: Haoxing Ren, Matthew Rudolph Fojtik
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Patent number: 12170757Abstract: Disclosed are apparatuses, systems, and techniques for real-time codec encoding of video files using hardware-assisted accelerators that utilize a combination of parallel and sequential processing, in which at least a part of intra-frame block prediction is performed with parallel processing.Type: GrantFiled: October 22, 2021Date of Patent: December 17, 2024Assignee: NVIDIA CorporationInventors: Ranga Ramanujam Srinivasan, Jianjun Chen, Dong Zhang, Wei Feng, Xi He
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Patent number: 12169882Abstract: Embodiments of the present disclosure relate to learning dense correspondences for images. Systems and methods are disclosed that disentangle structure and texture (or style) representations of GAN synthesized images by learning a dense pixel-level correspondence map for each image during image synthesis. A canonical coordinate frame is defined and a structure latent code for each generated image is warped to align with the canonical coordinate frame. In sum, the structure associated with the latent code is mapped into a shared coordinate space (canonical coordinate space), thereby establishing correspondences in the shared coordinate space. A correspondence generation system receives the warped coordinate correspondences as an encoded image structure. The encoded image structure and a texture latent code are used to synthesize an image. The shared coordinate space enables propagation of semantic labels from reference images to synthesized images.Type: GrantFiled: September 1, 2022Date of Patent: December 17, 2024Assignee: NVIDIA CorporationInventors: Sifei Liu, Jiteng Mu, Shalini De Mello, Zhiding Yu, Jan Kautz
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Publication number: 20240411977Abstract: Lattice graph routability modelling mechanisms for standard cells utilizing a trained lattice graph routability model to determine routability metrics for local areas and global net connections in the standard cell. The metrics are applied to influence transistor placement in the standard cell, resulting in standard cell layouts with improved routability. Circuit layout generating processes are also described, in which a layout is formed lacking external pin assignments, and during routing of the nets for the circuit, a graph comprising virtual nodes and edges from the virtual nodes to grid locations for pins external to the circuit is generated. Routing to the external net of the circuit is performed according to the graph nodes and the graph edges.Type: ApplicationFiled: June 6, 2023Publication date: December 12, 2024Applicant: NVIDIA Corp.Inventors: Chia-Tung HO, Haoxing Ren
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Publication number: 20240411974Abstract: Lattice graph routability modelling mechanisms for standard cells utilizing a trained lattice graph routability model to determine routability metrics for local areas and global net connections in the standard cell. The metrics are applied to influence transistor placement in the standard cell, resulting in standard cell layouts with improved routability. Circuit layout generating processes are also described, in which a layout is formed lacking external pin assignments, and during routing of the nets for the circuit, a graph comprising virtual nodes and edges from the virtual nodes to grid locations for pins external to the circuit is generated. Routing to the external net of the circuit is performed according to the graph nodes and the graph edges.Type: ApplicationFiled: June 6, 2023Publication date: December 12, 2024Applicant: NVIDIA Corp.Inventors: Chia-Tung HO, Haoxing Ren
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Patent number: 12164599Abstract: Volumetric quantification can be performed for various parameters of an object represented in volumetric data. Multiple views of the object can be generated, and those views provided to a set of neural networks that can generate inferences in parallel. The inferences from the different networks can be used to generate pseudo-labels for the data, for comparison purposes, which enables a co-training loss to be determined for the unlabeled data. The co-training loss can then be used to update the relevant network parameters for the overall data analysis network. If supervised data is also available then the network parameters can further be updated using the supervised loss.Type: GrantFiled: August 9, 2023Date of Patent: December 10, 2024Assignee: NVIDIA CorporationInventors: Holger Roth, Yingda Xia, Dong Yang, Daguang Xu
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Patent number: 12162418Abstract: In various examples, systems and methods are disclosed that accurately identify driver and passenger in-cabin activities that may indicate a biomechanical distraction that prevents a driver from being fully engaged in driving a vehicle. In particular, image data representative of an image of an occupant of a vehicle may be applied to one or more deep neural networks (DNNs). Using the DNNs, data indicative of key point locations corresponding to the occupant may be computed, a shape and/or a volume corresponding to the occupant may be reconstructed, a position and size of the occupant may be estimated, hand gesture activities may be classified, and/or body postures or poses may be classified. These determinations may be used to determine operations or settings for the vehicle to increase not only the safety of the occupants, but also of surrounding motorists, bicyclists, and pedestrians.Type: GrantFiled: October 5, 2023Date of Patent: December 10, 2024Assignee: NVIDIA CorporationInventors: Atousa Torabi, Sakthivel Sivaraman, Niranjan Avadhanam, Shagan Sah
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Patent number: 12165258Abstract: One or more machine learning models (MLMs) may learn implicit 3D representations of geometry of an object and of dynamics of the object from performing an action on the object. Implicit neural representations may be used to reconstruct high-fidelity full geometry of the object and predict a flow-based dynamics field from one or more images, which may provide a partial view of the object. Correspondences between locations of an object may be learned based at least on distances between the locations on a surface corresponding to the object, such as geodesic distances. The distances may be incorporated into a contrastive learning loss function to train one or more MLMs to learn correspondences between locations of the object, such as a correspondence embedding field. The correspondences may be used to evaluate state changes when evaluating one or more actions that may be performed on the object.Type: GrantFiled: March 10, 2022Date of Patent: December 10, 2024Assignee: NVIDIA CorporationInventors: Yuke Zhu, Bokui Shen, Christopher Bongsoo Choy, Animashree Anandkumar
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Patent number: 12164059Abstract: A deep neural network(s) (DNN) may be used to detect objects from sensor data of a three dimensional (3D) environment. For example, a multi-view perception DNN may include multiple constituent DNNs or stages chained together that sequentially process different views of the 3D environment. An example DNN may include a first stage that performs class segmentation in a first view (e.g., perspective view) and a second stage that performs class segmentation and/or regresses instance geometry in a second view (e.g., top-down). The DNN outputs may be processed to generate 2D and/or 3D bounding boxes and class labels for detected objects in the 3D environment. As such, the techniques described herein may be used to detect and classify animate objects and/or parts of an environment, and these detections and classifications may be provided to an autonomous vehicle drive stack to enable safe planning and control of the autonomous vehicle.Type: GrantFiled: July 15, 2021Date of Patent: December 10, 2024Assignee: NVIDIA CorporationInventors: Nikolai Smolyanskiy, Ryan Oldja, Ke Chen, Alexander Popov, Joachim Pehserl, Ibrahim Eden, Tilman Wekel, David Wehr, Ruchi Bhargava, David Nister
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Patent number: 12167169Abstract: A digital avatar system can process video streams and generate synthetic video with a digital avatar. The digital avatar provides the appearance of a participant from the video stream talking and one or more of performing various behaviors or actions consistent with the participant's behavior when they are live streamed. A digital avatar system can detect triggering events during a live stream and automatically switch to an avatar mode.Type: GrantFiled: September 19, 2022Date of Patent: December 10, 2024Assignee: NVIDIA CorporationInventors: Siddha Ganju, Ruthie Lyle, Naveen Kumar Rai, Ronay Ak, Andrew Russell
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Publication number: 20240402740Abstract: Power supply circuits in which a supplemental current driver is utilized to boost the current provided by a voltage regulator. The supplementing driver detects operating conditions for providing the supplementary current, and may be trained to provide particular amounts of current in response to particular operation conditions of a circuit load.Type: ApplicationFiled: June 1, 2023Publication date: December 5, 2024Applicant: NVIDIA Corp.Inventors: Zhonghua Li, Wen-Hung Lo, Michael Ivan Halfen, Abhishek Dhir, Jaewon Lee, Jiwang Lee, CHUNJEN SU
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Publication number: 20240400101Abstract: In various examples, systems and methods are disclosed relating to refinement of safety zones and improving evaluation metrics for the perception modules of autonomous and semi-autonomous systems. Example implementations can exclude areas in the state space that are not safety critical, while retaining the areas that are safety-critical. This can be accomplished by leveraging ego maneuver information and conditioning safety zone computations on ego maneuvers. A maneuver-based decomposition of perception safety zones may leverage a temporal convolution operation with the capability to account for collision at any intermediate time along the way to maneuver completion. This provides a significant reduction in zone volume while maintaining completeness, thus optimizing or otherwise enhancing obstacle perception performance requirements by filtering out regions of state space not relevant to a system's route of travel.Type: ApplicationFiled: June 2, 2023Publication date: December 5, 2024Applicant: NVIDIA CorporationInventors: Sever Ioan TOPAN, Yuxiao CHEN, Edward FU SCHMERLING, Karen Yan Ming LEUNG, Hans Jonas NILSSON, Michael COX, Marco PAVONE
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Patent number: 12159342Abstract: Ray tracing hardware accelerators supporting motion blur and moving/deforming geometry are disclosed. For example, dynamic objects in an acceleration data structure are encoded with temporal and spatial information. The hardware includes circuitry that test ray intersections against moving/deforming geometry by applying such temporal and spatial information. Such circuitry accelerates the visibility sampling of moving geometry, including rigid body motion and object deformation, and its associated moving bounding volumes to a performance similar to that of the visibility sampling of static geometry.Type: GrantFiled: May 20, 2022Date of Patent: December 3, 2024Assignee: NVIDIA CorporationInventors: Gregory Muthler, John Burgess
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Patent number: 12159694Abstract: A machine learning framework is described for performing generation of candidate molecules for, e.g., drug discovery or other applications. The framework utilizes a pre-trained encoder-decoder model to interface between representations of molecules and embeddings for those molecules in a latent space. A fusion module is located between the encoder and decoder and is used to fuse an embedding for an input molecule with embeddings for one or more exemplary molecules selected from a database that is constructed according to a design criteria. The fused embedding is decoded using the decoder to generate a candidate molecule. The fusion module is trained to reconstruct a nearest neighbor to the input molecule from the database based on the sample of exemplary molecules. An iterative approach may be used during inference to dynamically update the database to include newly generated candidate molecules.Type: GrantFiled: July 17, 2023Date of Patent: December 3, 2024Assignee: NVIDIA CorporationInventors: Weili Nie, Zichao Wang, Chaowei Xiao, Animashree Anandkumar
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Patent number: 12160498Abstract: Processors, systems and methods are described that synchronize clocks of devices on a second network that uses a second network protocol to a source clock on a first network that uses a first network protocol. Processors, systems and methods are described to cause a first time synchronization message corresponding to a first network communication protocol to be converted to a second time synchronization message corresponding to a second network communication protocol to enable synchronization.Type: GrantFiled: November 18, 2022Date of Patent: December 3, 2024Assignee: NVIDIA CorporationInventors: Ayal Lior, Ortal Bashan