Abstract: A method of handling messages at a user equipment received from a communications network during a procedure, the method implemented at the user equipment comprising: receiving a first message from the network whilst the user equipment is in a first operating state; processing the first message and entering a second operating state in response to receiving the first message; receiving a second message from the network whilst the user equipment is in the second operating state; detecting that the second message is a duplicate of the first message; and checking for an indication that the second message is a potential duplicate of the first message. If the indication is not present, the method further comprises transmitting a failure notification to the network. If the indication is present, the method further comprises discarding the second message and not transmitting a failure notification to the network to prevent failure of the procedure.

Abstract: A system, method, and computer program product are provided for utilizing a wavefront path tracer. In use, a set of light transport paths associated with a scene is identified. Additionally, parallel path tracing is performed, utilizing a wavefront path tracer.

Abstract: An integrated circuit package includes an interposer and an integrated circuit die. The interposer is formed from a layer of semiconductor material that is separated from a bulk portion of a semiconductor substrate, and the integrated circuit die is coupled to the interposer. Vias in the interposer can be formed in the thin layer of semiconductor material removed from the semiconductor substrate, and therefore can be scaled down significantly in size. Such reduced-size, through-interposer vias can be etched and filled much more cost-effectively and result in greatly reduced parasitic capacitance in the integrated circuit package.

Abstract: One embodiment sets forth a method for assigning priorities to kernels launched by a software application and executed within a stream of work on a parallel processing subsystem that supports dynamic parallelism. First, the software application assigns a maximum nesting depth for dynamic parallelism. The software application then assigns a stream priority to a stream. These assignments cause a driver to map the stream priority to a device priority and, subsequently, associate the device priority with the stream. As part of the mapping, the driver ensures that each device priority is at least the maximum nesting depth higher than the device priorities associated with any lower priority streams. Subsequently, the driver launches any kernel included in the stream with the device priority associated with the stream. Advantageously, by strategically assigning the maximum nesting depth and prioritizing streams, an application developer may increase the overall processing efficiency of the software application.

Abstract: In one embodiment the modem has a network interface, application interface, processor, and memory. The network interface exchanges radio data with a network. The application (or host) interface exchanges application data with an application (or host) processor. The processor converts a unit of radio data to a corresponding unit of application data. The memory stores each unit of application data received by the modem. The processor is configured to execute a selective discard function to reduce traffic by determining if a newly arrived unit of application data is a duplicate of a stored unit of application. In the case that the newly arrived unit of application data is a duplicate of the stored unit of application data, the processor is further configured to selectively discard the duplicate unit of application data in dependence on whether an acknowledgement of the data has been already recognized by the processor.

Abstract: Provided is a dual band antenna. The dual band antenna, in this aspect, includes an active element, the active element having a first resonant portion operable to effect a first antenna for communication in a first band of frequencies, and a second resonant portion operable to effect a second antenna for communication in a second different band of frequencies. The dual band antenna, of this aspect, further includes a ground element. In this aspect, the ground element and active element are structurally equivalent or functionally equivalent.

Abstract: One aspect provides a method of operating a modem at a terminal. The modem is arranged to store one or more message identifier. Each of the one or more message identifier identifies a type of message that the modem is arranged to act upon when received on a broadcast channel from a communications network. The method comprises detecting a country that the terminal is located in. The method further comprises determining if the detected country is a country in which a public warning system is implemented. The method further comprises determining if the one or more message identifier includes only public warning message identifiers. The method further comprises disabling monitoring of the broadcast channel if the detected country is not a country in which a public warning system is implemented and the one or more message identifier includes only public warning message identifiers.

Abstract: In an aspect there is provided a method of moving a processor of a mobile device from a low-power state for conserving power to an active mode for processing signals. The mobile device is configured to receive regularly scheduled signals. The method comprises, for each of multiple operating states of the mobile device determining a restore time associated with the operating state of the mobile device and storing each determined restore time in association with its operating state. The method further comprises detecting a current operating state of the mobile device and using the determined restore time for that state to set a trigger time to control movement of the processor of the mobile device to enter the active mode from the low-power mode in time to process the scheduled signals.

Abstract: Provided, in one aspect, is an antenna. The antenna, in this aspect, includes an active element, the active element having a resonant portion operable to effect an antenna for communication in a band of frequencies. The antenna, of this aspect, further includes a ground element. In this aspect, the ground element and active element are structurally equivalent or functionally equivalent.

Abstract: One embodiment sets forth a method for assigning priorities to kernels launched by a software application and executed within a stream of work on a parallel processing subsystem. First, the software application assigns a desired priority to a stream using a call included in the API. The API receives this call and passes it to a driver. The driver maps the desired priority to an appropriate device priority associated with the parallel processing subsystem. Subsequently, if the software application launches a particular kernel within the stream, then the driver assigns the device priority associated with the stream to the kernel before adding the kernel to the stream for execution on the parallel processing subsystem. Advantageously, by assigning priorities to streams and, subsequently, strategically launching kernels within the prioritized streams, an application developer may fine-tune the software application to increase the overall processing efficiency of the software application.

Abstract: An integrated circuit package includes an integrated circuit package comprising an interposer and an integrated circuit die. The interposer is formed from a silicon-on-insulator semiconductor substrate and includes a plurality of through-silicon vias, and the integrated circuit die is electrically coupled to a first through-silicon via included in the plurality of through-silicon vias. Through-silicon vias in the integrated circuit package can be formed in the thin silicon surface layer of the silicon-on-insulator substrate, and therefore can be scaled down significantly in size. Such reduced-size through-silicon vias can be etched and filled much more cost-effectively and result in greatly reduced parasitic capacitance in the integrated circuit package.

Abstract: A graphics system and a multi-user computer system are disclosed. The graphics system comprises a graphics processing unit (GPU) for processing pixels. It further includes a multi-user manager for allocating pixel processing capability for each one of a plurality of users, wherein each user uses a display and an input device. Moreover, the graphics system has a plurality of user attributes for each user. The multi-user computer system comprises a central processing unit (CPU) and a disk drive configured to support a plurality of users. Further, the multi-user computer system includes the graphics system.

Abstract: A method of authorizing access to content, in accordance with one embodiment of the present invention, includes receiving a request to access an instance of content. A key registry server may provide user accounts, which identify an authorized user of the instance of content and a parameter for accessing the instance of content. A determination is then made that accessing the instance of content is within the parameter and authorized for the user and access to the instance of content is allowed. The content may be local to the use system or accessed remotely (e.g., over a network). Also, the registry may be remote to the user system or local or both (e.g., with updates periodically made).

Abstract: A clock gating latch, a method of gating a clock signal and an integrating circuit incorporating the clock gating latch or the method. In one embodiment, the clock gating latch includes: (1) a propagation circuit having a single, first switch configured to be driven by an input clock signal, (2) a keeper circuit coupled to the propagation circuit and having a single, first switch configured to be driven by the input clock signal and (3) an AND gate coupled to the propagation circuit and the keeper circuit and having an internal node coupled to a second switch in the propagation circuit and a second switch in the keeper circuit.

Abstract: A system, method, and computer program product for scheduling tasks associated with continuation thread blocks. The method includes the steps of generating a first task metadata data structure in a memory, generating a second task metadata data structure in the memory, executing a first task corresponding to the first task metadata data structure in a processor, generating state information representing a continuation task related to the first task and storing the state information in the second task metadata data structure, executing the continuation task in the processor after the one or more child tasks have finished execution, and indicating that the first task has logically finished execution once the continuation task has finished execution. The second task metadata data structure is related to the first task metadata data structure, and at least one instruction in the first task causes one or more child tasks to be executed by the processor.

Abstract: A method of providing an application to a user device, a method of managing static assets for applications and an asset management system are disclosed herein. In one aspect, the method of providing an application to a user device includes: (1) receiving a request from a user device to download an application, (2) sending a manifest of the application to the user device, the manifest including a list of asset keys for the application wherein each of the asset keys uniquely corresponds to a static asset of the application and (3) compiling, by a processor, a transmit list of the static assets that are absent from the user device.

Abstract: A system, method, and computer program product for low-latency scheduling and launch of memory defined tasks. The method includes the steps of receiving a task metadata data structure to be stored in a memory associated with a processor, transmitting the task metadata data structure to a scheduling unit of the processor, storing the task metadata data structure in a cache unit included in the scheduling unit, and copying the task metadata data structure from the cache unit to the memory.

Abstract: A phase-locked loop digital bandwidth calibrator includes a digital loop filter having a gain multiplier memory and a perturbation unit configured to generate a calibration offset signal to initiate a calibration. Additionally, the phase-locked loop digital bandwidth calibrator also includes a digital bandwidth calibration unit configured to provide a corrected nominal gain for storage in the gain multiplier memory, wherein a digital gain correction for the corrected nominal gain is determined by a digital integration stage and a correction database. A phase-locked loop digital bandwidth calibration method is also provided.

Abstract: An approach is provided for managing multichannel playback of audio data over a wireless network. In one example, a host device determines one or more client devices that are eligible to receive a transmission of the audio data over a wireless network from the host device for playback of the audio data. The host device displays the one or more client devices that are eligible. The host device receives a selection of at least one of the client devices. The host device establishes a connection to each of the selected client devices for the host device to transmit at least one channel of the audio data to each of the selected client devices over the wireless network. The host device displays a map of positions of the connected client devices.

Abstract: A graphical processing unit having an implementation of a hierarchical hash table thereon, a method of establishing a hierarchical hash table in a graphics processing unit and GPU computing system are disclosed herein. In one embodiment, the graphics processing unit includes: (1) a plurality of parallel processors, wherein each of the plurality of parallel processors includes parallel processing cores, a shared memory coupled to each of the parallel processing cores, and registers, wherein each one of the registers is uniquely associated with one of the parallel processing cores and (2) a controller configured to employ at least one of the registers to establish a hierarchical hash table for a key-value pair of a thread processing on one of the parallel processing cores.