Abstract: A shadow softening GPU and method. One embodiment of the GPU is configured to render a shadow cast by a surface occluding a light source and includes: (1) a fetching circuit operable to retrieve a depth value from a texture associated with the surface and a depth comparison result in a single fetch operation, and (2) a shadow softening circuit configured to respectively employ the depth comparison result and the depth value to identify the surface as a blocker and attenuate the light source for a pixel.

Abstract: One embodiment of a system for cooling a heat-generating device includes a base adapted to be coupled to the heat-generating device, a housing coupled to the base, a liquid channel formed between the base and the housing, where a heat transfer liquid may be circulated through the liquid channel to remove heat generated by the heat-generated device, and a heat pipe disposed within the liquid channel, where the heat pipe increases the heat transfer surface area to which the heat transfer liquid is exposed. Among other things, the heat pipe advantageously increases the heat transfer surface area to which the heat transfer liquid is exposed and efficiently spreads the heat generated by the heat-generating device over that heat transfer surface area. The result is enhanced heat transfer through the liquid channel relative to prior art cooling systems.

Abstract: A method includes storing data related to a video frame or an image separately from data related to a subtitle of the video frame or the image in a memory of a data processing device, and comparing, through a processor communicatively coupled to the memory, a color parameter of the data related to the video frame or the image to a color parameter of the data related to the subtitle. The method also includes dynamically adjusting a color parameter of at least a portion of the data related to the subtitle and/or a color parameter of at least a portion of the data related to the video frame or the image based on the comparison. Further, the method includes overlaying the data related to the subtitle on the data related to the video frame or the image following the dynamic adjustment prior to rendering thereof on a display unit.

Abstract: A system and method for buffering intermediate data in a processing pipeline architecture stores the intermediate data in a shared cache that is coupled between one or more pipeline processing units and an external memory. The shared cache provides storage that is used by multiple pipeline processing units. The storage capacity of the shared cache is dynamically allocated to the different pipeline processing units as needed, to avoid stalling the upstream units, thereby improving overall system throughput.

Abstract: Using fewer bits to indicate the prediction mode used for encoding some of the non-frame-edge blocks of a frame. In an embodiment, fewer bits are used in case of boundary blocks of a slice, or slice group. In another embodiment, fewer bits are used when adjacent blocks are encoded using inter-frame coding or switchable intra-frame coding and such adjacent block cannot be used in predicting a block.

Abstract: A system, method, and computer program product are provided for performing shadowing utilizing shadow maps and ray tracing. In operation, one or more shadow maps are rendered for at least one light source. Additionally, low confidence pixels associated with the one or more shadow maps are determined. Furthermore, shadow rays associated with the low confidence pixels are traced.

Abstract: A method and a system are provided for controlling memory accesses. Memory access requests including at least a first speculative memory access request and a first non-speculative memory access request are received and a memory access request is selected from the memory access requests. A memory access command is generated to process the selected memory access request.

Abstract: A method comprises adapting a first tap weight of an equalizer, wherein a second tap weight of the equalizer is based at least in part on the first tap weight. Adapting the first tap weight further comprises computing a gradient from a data signal, an error signal and a channel pulse response sample. Adapting the first tap weight also comprises filtering the gradient with a loop filter and sending information to a transmitter via a back channel. Adapting the first tap weight further comprises configuring the first tap weight based on the information.

Abstract: A system and method are provided for controlling a soft-switched modified buck regulator circuit. A voltage (Vx) across or a current through a pull-down switching mechanism within the modified buck regulator circuit is sensed when the pull-down switching mechanism is enabled, where the pull-down switching mechanism is coupled to an upstream end of an inductor and is coupled in parallel with a capacitor. A target time when the pull-down switching mechanism will be disabled (tlf) is computed and the pull-down transistor is disabled at the computed target time.

Abstract: One embodiment of the present invention sets for a method for monitoring the aging of a circuit. The method includes operating an aging unit included in the circuit beginning at a first time. The method also includes in response to a trigger event, operating a non-aging unit also included in the circuit beginning at a second time wherein the second time is subsequent to the first time. The method further includes detecting a frequency difference between a first frequency generated by the aging unit and a second frequency generated by the non-aging unit. The method also includes generating a modified power supply voltage based on the frequency difference. The method also includes applying the modified power supply voltage to the non-aging unit.

Abstract: A system, method, and computer program product are provided for performing path space filtering. In use, a set of light transport paths associated with a scene is sampled. Additionally, a plurality of vertices associated with the sampled set of light transport paths is selected, where each selected vertex has an associated throughput and light contribution. Further, an averaged light contribution of each of the selected plurality of vertices is determined, utilizing one or more weights. Further still, the averaged light contribution of each of the selected plurality of vertices is combined after multiplying the averaged light contribution of each of the selected vertices by the associated throughput of the vertex.

Abstract: One embodiment sets forth a method for efficiently determining memory resource dependencies between instructions included in a software application. For each instruction, a dependency analyzer uses overlapping search techniques to identify one or more overlaps between the memory elements included in the current instruction and the memory elements included in previous instructions. The dependency analyzer then maps objects included in the instructions to a set of partition elements wherein each partition element represents a set of memory elements that are functionally equivalent for dependency analysis. Subsequently, the dependency analyzer uses the set of partition elements to determine memory dependencies between the instructions at the memory element level.

Abstract: One embodiment sets forth a method for efficiently determining memory resource dependencies between instructions included in a software application. For each instruction, a dependency analyzer uses overlapping search techniques to identify one or more overlaps between the memory elements included in the current instruction and the memory elements included in previous instructions. The dependency analyzer then maps objects included in the instructions to a set of partition elements wherein each partition element represents a set of memory elements that are functionally equivalent for dependency analysis. Subsequently, the dependency analyzer uses the set of partition elements to determine memory dependencies between the instructions at the memory element level.

Abstract: A static random access memory (SRAM) cell is disclosed. The SRAM cell includes a storage unit configured to store a data bit in a storage node. The SRAM cell further includes an access unit coupled to the storage unit. The access unit is configured to transfer current to the storage node when a word line is asserted. The SRAM cell further includes a row header configured to provide current from a power supply when the word line is not asserted, and to not provide current from the power supply when the word line is asserted. The SRAM cell further includes a column header configured to provide current from a power supply when a write column line is not asserted, and to not provide current from the power supply when the write column line is asserted.

Abstract: A system and method are provided for controlling a multi-phase switching regulator including a first phase and a second phase, where the first phase includes a first modified buck regulator circuit and the second phase includes a second modified buck regulator circuit. The first phase and the second phase are activated. The first phase is operated in a soft-switching mode to provide current to a load for a first portion of an operating cycle and the second phase is operated in a soft-switching mode to provide current to the load for a second portion of the operating cycle.

Abstract: Various embodiments relating to executing different types of instruction code in a micro-processing system are provided.

Abstract: A secure virtual machine system, method, and computer program product implemented on a processor are provided for processing a third party's content for output. At least one processor is provided. Additionally, at least one secure virtual machine implemented on the processor is provided for interpreting a second party's program that processes and outputs a third party's content. The virtual machine system abstracts the underlying processor hardware allowing implementation variations across products to execute the same program identically. Furthermore, the scope of the programmable operations, the types of input & output variables, and execution of programs within the processor, is deliberately constrained within the virtual machine environment, in order to mitigate potential security leaks by programs, and to ensure confidentiality of second party's secrets, and third party's content as managed by the second party's program.

Abstract: One embodiment of the invention sets forth a mechanism for evicting data from a data cache based on the data class of that data. The data stored in the cache lines in the data cache is categorized based on data classes that reflect the reuse potential of that data. The data classes are stored in a tag store, where each tag within the tag store corresponds to a single cache line within the data cache. When reserving a cache line for the data associated with a command, a tag look-up unit examines the data classes in the tag store to determine which data to evict. Data that has a low reuse potential is evicted at a higher priority than data that has a high reuse potential. Advantageously, evicting data that belongs to a data class that has a lower reuse potential reduces the number of cache misses within the system.

Abstract: A mobile terminal comprising: transceiver apparatus for accessing a wireless network using an earlier and a later generation radio access technology, to establish a voice channel and packet data channel; and an inter radio access technology selector configured to monitor a condition for disabling the earlier generation access, being a condition other than coverage under the earlier generation technology falling below an acceptable lower level. The selector makes inter radio access technology decisions dynamically from the mobile terminal by updating registration with the network to indicate that the earlier generation technology is no longer supported. The selector thereby prevents the mobile terminal being subject to decisions from the network that would otherwise impose transfer to the earlier generation. At least some of the decisions made from the mobile terminal thus disable the earlier generation access whilst in presence of at least the lower level of coverage under the earlier generation.

Abstract: A method and a system are provided for clock phase detection. A first set of delayed versions of a first clock signal is generated and a second set of delayed versions of a second clock signal is generated. The second set of delayed versions of the second clock signal is sampled using the first set of delayed versions of the first clock signal to produce an array of clock samples in a domain corresponding to the first clock signal. At least one edge indication is located within the array of clock samples.