Abstract: A video navigation system and method can be utilized to efficiently and adjustably navigate video content. In one embodiment, a video information control method facilitates efficient video navigation. A video stream is received and video access point selection between multiple access points in said video stream is controlled. The presentation information is forwarded for each of the multiple access points. In one exemplary implementation, the presentation information is forwarded to a display and the information is directed to presenting a main viewing area and navigation areas that present looping video clips or portions of the video stream at time intervals ahead of and behind the video portion being presented in the main viewing area.

Abstract: A scalable discrete graphics system (DGS) is disclosed. The DGS includes a serial bus bridge configured to couple a plurality of GPUs to a serial bus. A serial bus connector is coupled to the serial bus bridge. A system chassis coupled to the serial bus bridge and the serial bus connector and configured to house the GPUs. The serial bus connector is configured to removably connect to a computer system. The GPUs access the computer system via the serial bus bridge and the serial bus connector to cooperatively execute 3-D graphics instructions from the computer system.

Abstract: One embodiment sets forth a timing calibration technique for on-chip source-synchronous, complementary metal-oxide-semiconductor (CMOS) repeater-based interconnect. Two transition patterns may be applied to calibrate the delay of an on-chip data or clock wire. Calibration logic is configured to apply the transition patterns and then trim the delays of the clock and data wires based on captured calibration patterns. The trimming adjusts the delay of the clock and data wires using a configurable delay circuit. Timing errors may be caused by crosstalk, power-supply-induced jitter (PSIJ), or wire delay variation due to transistor and wire metallization mismatch. Chip yields may be improved by reducing the occurrence of timing errors due to mismatched delays between different wires of an on-chip interconnect.

Abstract: Embodiments of the present disclosure provide techniques for identifying a display when a graphics processing unit (GPU) connected to the display via a display control bus is in a low power state. By providing a separate microcontroller with a parallel connection to the display control bus, the microcontroller may detect the presence of a display device even when the GPU is in the low power state. In response to detecting the display device, the microcontroller may notify a motherboard chipset (e.g., via an interrupt) prompting the motherboard chipset to initiate a sequence to bring the GPU out of the low power state.

Abstract: One embodiment of the present invention includes a graphics subsystem for processing multi-sample anti-aliasing work. The graphics subsystem includes a cache unit, a tiling unit, and a screen-space pipeline coupled to the cache unit and to the tiling unit. The tiling unit is configured to organize multi-sample anti-aliasing commands into cache tile batches. The screen-space pipeline includes a pixel shader and a raster operations unit, and receives cache tile batches from the tiling unit. The pixel shader is configured to generate sample data based on a set of primitives and to generate resolved data based on the sample data. The raster operations unit is configured to store the sample data in the cache unit and to invalidate the sample data after the pixel shader generates the resolved data.

Abstract: A system is based on an IC. A first component of the IC generates a signal that clocks the IC at a target operating frequency. A period corresponding to the target clock frequency exceeds a duration of a longest critical path associated with the IC. The first component and synchronous logic of the IC clocked therewith, each functions with the core supply voltage, which may be supplied to each via the same power supply rail. A second IC component detects errors that relate to an operation of the IC at the target clock frequency and determines a level for adjusting the core supply voltage. The Vdd adjustment ameliorates the frequency error. The voltage determination uses closed loop dynamic voltage and frequency scaling.

Abstract: A method, system and computer program product embodied on a computer-readable medium are provided for managing the execution of out-of-order instructions. The method includes the steps of receiving a plurality of instructions and identifying a subset of instructions in the plurality of instructions to be executed out-of-order.

Abstract: Embodiments of the present invention are capable of determining a face direction associated with a detected subject (or multiple detected subjects) of interest within a 3D space using face detection procedures, while simultaneously avoiding the pick up of other environmental sounds. In addition, if more than one face is detected, embodiments of the present invention can automatically detect an active speaker based on the recognition of facial movements consistent with the performance of providing audio (e.g., tracking mouth movements) by those subjects whose faces were detected. Once determinations are made regarding face direction of the detected subject, embodiments of the present invention may dynamically adjust the audio acquisition capabilities of the audio capture device (e.g., microphone devices) relative to the location of the detected subject using beamforming techniques for instance.

Abstract: One embodiment includes determining a first z-range for a first portion of a coarse raster tile, where the first portion includes a plurality of pixels having a first set of pixel locations, retrieving from a memory a corresponding z-range related to a second set of pixel locations associated with the coarse raster tile, where the first set of pixel locations comprises a subset of the second set of pixel locations, and comparing the first z-range to the corresponding z-range to determine whether the plurality of pixels is occluded. If the plurality of pixels determined to be occluded, then the plurality of pixels is culled. If the plurality of pixels is determined to not be occluded, then the plurality of pixels is transmitted to a fine raster unit for further processing. The coarse raster tile comprises a plurality of portions, including the first portion, and those portions are processed serially.

Abstract: Provided is an antenna system. The antenna system, in this aspect, includes a first antenna operable to communicate at a given frequency below about 1000 MHz. The antenna system, in this aspect, further includes a second antenna of a different type associated with the first antenna and operable to communicate at the given frequency, wherein a correlation coefficient of the first and second antennas is less than about 0.5 for the given frequency. In this antenna system, the first and second antennas are capable of fitting within a conductive chassis having a largest physical dimension of about ¼ or less a wavelength of the given frequency.

Abstract: A technique for ensuring that multiple producer threads may simultaneously write entries in a shared queue and one or more consumers may read valid data from the shared queue. Writing of the shared queue by the multiple producer threads may occur in parallel and the one or more consumer threads may read the shared queue while the producer threads write the shared queue. A “wait-free” mechanism allows any producer thread that writes a shared queue to advance an inner pointer that is used by a consumer thread to read valid data from the shared queue. The inner pointer indicates the most recent valid entry. An output pointer is advanced with an atomic operation to indicate a next entry or portion of memory in the shared queue that is available for allocation. The shared queue may be implemented as a circular buffer.

Abstract: An application programming interface (API) executed by a first processing unit combines audio data samples with error code values generated for those samples. The API then causes a data stream to be opened having sufficient bandwidth to accommodate combined samples made up of audio data samples and corresponding error code values. The combined samples are then transmitted to a decoder and validation unit within a second processing unit that receives the combined data, strips the error code values and validates the audio data based on the error code values. When the error code values indicate that the audio data has been compromised, the second processing unit terminates the output of sound derived from the audio data.

Abstract: One embodiment of the present invention sets forth a technique for performing fast integer division using commonly available arithmetic operations. The technique may be implemented in a four-stage process using a single-precision floating point reciprocal in conjunction with integer addition and multiplication. Furthermore, the technique may be fully pipelined on many conventional processors for overall performance that is comparable to the best available high-performance alternatives.

Abstract: Rendered image data is encoded by a server computing device and transmitted to a remote client device that executes an interactive application program. The client device decodes and displays the image data and, when the user interacts with the application program, the client device provides input control signals to the server computing device. When input control signals are received by the server, the latency incurred for encoding and/or decoding the image data is reduced. Therefore, the user does not experience inconsistencies in the frame rate of images displayed on the client when the user interacts with the application program. The reduction in latency is achieved by dynamically switching from a hardware implemented encoding technique to a software implemented encoding technique. Latency may also be reduced by dynamically switching from a hardware implemented decoding technique to a software implemented decoding technique.

Abstract: One embodiment sets forth a method for associating each stencil value included in a stencil buffer with multiple fragments. Components within a graphics processing pipeline use a set of stencil masks to partition the bits of each stencil value. Each stencil mask selects a different subset of bits, and each fragment is strategically associated with both a stencil value and a stencil mask. Before performing stencil actions associated with a fragment, the raster operations unit performs stencil mask operations on the operands. No fragments are associated with both the same stencil mask and the same stencil value. Consequently, no fragments are associated with the same stencil bits included in the stencil buffer. Advantageously, by reducing the number of stencil bits associated with each fragment, certain classes of software applications may reduce the wasted memory associated with stencil buffers in which each stencil value is associated with a single fragment.

Abstract: One embodiment of the present invention sets forth an architecture for advancing the Z-test operation prior to pixel shading whenever possible. The current rendering state, as maintained by the setup engine, determines whether advancing the Z-test function above the shader engine for “early” Z-testing is possible or whether the Z-test function should be deferred until after shading operations for “late” Z-testing. Data is dynamically routed to each processing engine in the pipeline, so that the appropriate data flow for either early Z or late Z is dynamically constructed, as determined by the current rendering state. The same functional units are utilized in both early Z and late Z configurations.

Abstract: A method and system for vector processor quantization acceleration for an encoding process. The encoding process is implemented using the hardware of a video processor. The method includes computing coefficients for a DCT (discrete cosine transform) encoding operation and determining a quantization step for use with a quantization operation for each of the coefficients. A vector processor is then used for quantization acceleration. Out of a range of possible quantized output values, the vector processor computes a set of quantized output values from the coefficients. The vector processor is configured to evaluate each of the quantized output values of the set in parallel. For the range of possible quantized output values that are not computed using the vector processor, the quantized output values are computed by using a multiplication logic path.

Abstract: A data connector includes two different sets of wires that transport data between components of a computer system. A first set of wires transports data from a first component to a second component. A second set of wires transports data from the second component to the first component. The first set of wires is interlaced with the second set of wires so that each wire in the data connector transports data in the opposite direction of one or more neighboring wires.

Abstract: A method, program and user equipment for wireless communication in a cellular communication system comprising a plurality of base stations. The method comprises: synchronizing to one of said the base stations using a synchronization channel transmitted from that base station; receiving a pilot channel from said base station; after synchronizing to said base station, receiving a signal from that base station; and using the pilot channel from said base station to cancel interference on said signal caused by the synchronization channel.

Abstract: An apparatus for providing graphics processing. The apparatus includes a dual CPU socket architecture comprising a first CPU socket and a second CPU socket. The apparatus includes a plurality of GPU boards providing a plurality of GPU processors coupled to the first CPU socket and the second CPU socket, wherein each GPU board comprises two or more of the plurality of GPU processors. The apparatus includes a communication interface coupling the first CPU socket to a first subset of one or more GPU boards and the second CPU socket to a second subset of one or more GPU boards.