Patents Assigned to NVidia
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Patent number: 8860742Abstract: A technique for caching coverage information for edges that are shared between adjacent graphics primitives may reduce the number of times a shared edge is rasterized. Consequently, power consumed during rasterization may be reduced. During rasterization of a first graphics primitive coverage information is generated that (1) indicates cells within a sampling grid that are entirely outside an edge of the first graphics primitive and (2) indicates cells within the sampling grid that are intersected by the edge and are only partially covered by the first graphics primitive. The coverage information for the edge is stored in a cache. When a second graphics primitive is rasterized that shares the edge with the first graphics primitive, the coverage information is read from the cache instead of being recomputed.Type: GrantFiled: May 2, 2012Date of Patent: October 14, 2014Assignee: NVIDIA CorporationInventors: Michael C. Shebanow, Anjul Patney
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Patent number: 8861290Abstract: A method and a system are provided for performing write assist. Write assist circuitry is initialized and voltage collapse is initiated to reduce a column supply voltage provided to a storage cell. A bitline of the storage cell is boosted to a boosted voltage level that is below a low supply voltage provided to the storage cell and data encoded by the bitline is written to the storage cell.Type: GrantFiled: December 10, 2012Date of Patent: October 14, 2014Assignee: NVIDIA CorporationInventors: Brian Matthew Zimmer, Mahmut Ersin Sinangil
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Patent number: 8858327Abstract: The present invention discloses a method and a device for providing a game. The method includes: a detection step, for determining an additional display device being attached to a mobile device; and a push step, for pushing multimedia information of the game to the additional display device to be presented by the additional display device, and pushing a visual human machine interface of the game to a display of the mobile device to be displayed by the display; wherein, a controlled object displayed on the additional display device is controlled by the visual human machine interface. The above-mentioned method and device for providing a game can make a game machine have a smaller size and be more portable, display multimedia information of a game on a bigger screen for players and provide players with a visual human machine interface on the entire screen of a mobile device, and therefore it improves user experiences.Type: GrantFiled: November 2, 2012Date of Patent: October 14, 2014Assignee: NVIDIA CorporationInventor: Fei Wang
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Patent number: 8861586Abstract: A decoder can include a first stage operable for decoding (prior to deblocking) an encoded frame, and second stage coupled downstream of the first stage. The second stage includes a first deblocker and a second deblocker that can be used to deblock decoded frames in parallel. Each decoded frame can be classified as a type of frame and is sent to one of the deblockers depending on its classification.Type: GrantFiled: October 14, 2008Date of Patent: October 14, 2014Assignee: Nvidia CorporationInventor: Wei Jia
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Patent number: 8860497Abstract: A reduced oxide stress cascode stack circuit includes a cascade transistor stack and dynamic bias circuits that supply an output voltage having a magnitude greater than an oxide reliability voltage of their component transistors. The reduced oxide stress cascode stack circuit also includes an offset voltage generator that provides an offset voltage based on a transient extreme of the output voltage, wherein the offset voltage is applied to the cascade transistor stack and the dynamic bias circuits to reduce component transistor voltages commensurate with the oxide reliability voltage. The reduced oxide stress cascode stack circuit further includes a bias voltage supply that modifies a bias voltage value of the cascade transistor stack and dynamic bias circuits by an amount proportional to the offset voltage. A method of reducing oxide stress in a cascode stack circuit is also provided.Type: GrantFiled: July 1, 2013Date of Patent: October 14, 2014Assignee: Nvidia CorporationInventors: Tapan Pattnayak, Shifeng Yu
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Patent number: 8860766Abstract: A system, method, and computer program product are provided for determining one or more contact points between a pair of objects. In operation, a first contact normal is identified between a pair of objects at a first position. Additionally, a relative velocity of the pair of objects is determined at the first position. Furthermore, one or more contact points between the pair of objects are determined at a second position through a translational analysis, utilizing the first contact normal and the relative velocity.Type: GrantFiled: September 30, 2010Date of Patent: October 14, 2014Assignee: NVIDIA CorporationInventor: Adam Moravanszky
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Patent number: 8862823Abstract: One embodiment of the present invention sets forth a compression status cache configured to store compression information for blocks of memory stored within an external memory. A data cache unit is configured to request, in response to a cache miss, compressed data from the external memory based on compression information stored in the compression status bit cache. The compression status for active buffers is dynamically swapped into the compression status cache as needed. Different compression formats may be specified for one or more tiles within an active buffer. One advantage of the disclosed compression status cache is that a lame amount of attached memory may be allocated as compressible memory blocks, without incurring a corresponding die area cost because a portion of the compression status stored off chip in attached memory is cached in the compression status cache.Type: GrantFiled: December 19, 2008Date of Patent: October 14, 2014Assignee: NVIDIA CorporationInventors: David B. Glasco, Cass W. Everitt, David Kirk Mcallister, Emmett M. Kilgariff, George R. Lynch, James Roberts, Karan Mehra, Patrick R. Marchand, Peter B. Holmqvist, Steven E. Molnar
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Publication number: 20140300624Abstract: A solution is proposed that performs global histogramming of pre-regionally-enhanced pixel values accounting for inter-regional illumination contributions to verify that over-saturation of an image is prevented. According to an embodiment, pixel values that have been regionally enhanced—that is, with applied gains calculated for the respective regions—are further added to illumination values corresponding to the pixel values, with the resultant summed pixel values being histogrammed again to determine the amount of over-saturated pixels. An over-abundance of over-saturated pixels results in a calculation of a global modifier applied to each pixel to reduce the number of over-saturated pixels below an acceptable threshold.Type: ApplicationFiled: April 4, 2013Publication date: October 9, 2014Applicant: NVIDIA CorporationInventor: David WYATT
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Publication number: 20140300778Abstract: Raw video data is captured, processed, and then stored within a set of buffers. An encoder engine is configured to encode the video data for storage. A feedback controller dynamically adjusts the clock frequency of the encoder engine based on the number of buffers currently occupied by the video data. The feedback controller is tuned so that the clock frequency of the encoder engine will be increased when the number of buffers occupied by video data increases, and the clock frequency of the encoder engine will be decreased when the number of buffers occupied by the video data decreases.Type: ApplicationFiled: April 5, 2013Publication date: October 9, 2014Applicant: NVIDIA CorporationInventor: Jihoon BANG
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Publication number: 20140302815Abstract: A method, in a wireless communications device, comprising: receiving a new security mode configuration from a radio access network that is to replace an original security mode configuration as part of a security procedure; detecting, prior to completion of said security procedure, that a cell update message is to be sent to the network; transmitting a first cell update message to the network in accordance with the original security mode configuration; transmitting a second cell update message to the network in accordance with the new security mode configuration; receiving a cell update confirm message, the cell update confirm message sent by the network in accordance with a network determined security mode configuration; ascertaining if the network determined security mode configuration is either the original or new security mode configuration; and completing the cell update procedure in accordance with the ascertained security mode configuration.Type: ApplicationFiled: April 5, 2013Publication date: October 9, 2014Applicant: NVIDIA CorporationInventor: Tim Rogers
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Publication number: 20140301134Abstract: A system is provided for transmitting signals. The system comprises a first processing unit, a cache memory, and a package. The first processing unit comprises a first ground-referenced single-ended signaling (GRS) interface circuit and the second processing unit comprises a second GRS interface circuit. The cache memory comprises a third and a fourth GRS interface circuit. The package comprises one or more electrical traces that couple the first GRS interface to the third GRS interface and couple the second GRS interface to the fourth GRS interface, where the first GRS interface circuit, the second GRS interface, the third GRS interface, and the fourth GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network.Type: ApplicationFiled: April 4, 2013Publication date: October 9, 2014Applicant: NVIDIA CorporationInventors: William J. Dally, John W. Poulton, Thomas Hastings Greer, III, Brucek Kurdo Khailany, Carl Thomas Gray
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Publication number: 20140300618Abstract: A solution is proposed that allows power savings via enhancement of pixel data to compensate for reducing backlight intensity levels. According to one embodiment, each pixel of a display is sorted according to the brightness (intensity) of the pixel. Regional pixel gains are calculated and applied on a per pixel basis so as not to exceed a quality threshold. The intensity of the backlight corresponding to each region may be decreased by an equivalent amount, thereby reducing (potentially significantly) the power consumed to operate the backlight while maintaining the color intensity in the image due to the applied pixel gains.Type: ApplicationFiled: April 4, 2013Publication date: October 9, 2014Applicant: NVIDIA CorporationInventor: David WYATT
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Publication number: 20140301658Abstract: An aspect of the present invention proposes a solution to allow low-cost flat panel displays without light guides to maintain a high quality image display via enhancement of pixel data to account for non uniform brightness. According to one embodiment, each pixel of a display is mapped to the brightness (intensity) of illumination that reaches the pixel. Regional pixel gains are calculated and applied on a per pixel basis to compensate for the non-uniform brightness across the screen. According to such an embodiment, even low cost flat panel displays experiencing non-uniform brightness can be used to render high quality images.Type: ApplicationFiled: April 4, 2013Publication date: October 9, 2014Applicant: NVIDIA CorporationInventor: David WYATT
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Publication number: 20140304417Abstract: In one aspect there is provided a host device having: a modem interface arranged to transmit transmission units between the host device and a modem; a communication function configured to generate primitives to establish a communication event between the host device and a remote device; a client agent connected to receive control primitives from the communication function and operable to convert the control primitives to data transmission units; a host routing interface operable to route data transmission units from the client agent according to a predetermined route option which is set based on whether a communication event control function for processing the data transmission units is located on the host device or the modem.Type: ApplicationFiled: April 4, 2013Publication date: October 9, 2014Applicant: NVIDIA CorporationInventors: Thomas Fleury, Flavien Delorme
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Patent number: 8854364Abstract: The range of depth values within the overlap of a convex polygon and a square or rectangular rasterization area can be determined by identifying whether the minimum and maximum depth values occur at the corners of the rasterization area or at intersections of the polygon's edges with the area's sides. By choosing between the corner and intersection for both the minimum and maximum depth limit, solving the depth plane equation at the chosen location, and clamping against the polygon's vertex depth range, a tight depth range describing the depth values within that overlap are obtained. That tight depth range is utilized to cull pixel values early in the pipeline, improving performance and power consumption.Type: GrantFiled: April 3, 2006Date of Patent: October 7, 2014Assignee: Nvidia CorporationInventor: Douglas A. Voorhies
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Patent number: 8854123Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a second processor chip, and an MCM package configured to include the first processor chip, the second processor chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first GRS interface circuit to the interconnect circuit. The second processor chip is configured to include a second GRS interface circuit. A second set of electrical traces fabricated within the MCM package and configured to coupled the second GRS interface circuit to the interconnect circuit.Type: GrantFiled: July 19, 2013Date of Patent: October 7, 2014Assignee: NVIDIA CorporationInventors: William J. Dally, Brucek Kurdo Khailany, John W. Poulton, Thomas Hastings Greer, III, Carl Thomas Gray
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Patent number: 8856499Abstract: An apparatus is disclosed. The apparatus comprises an instruction mapping table, which includes a plurality of instruction counts and a plurality of instruction pointers each corresponding with one of the instruction counts. Each instruction pointer identifies a next instruction for execution. Further, each instruction count specifies a number of instructions to execute beginning with the next instruction. The apparatus also has a data operation unit adapted to receive a data group and adapted to execute on the received data group the number of instructions specified by a current instruction count of the instruction mapping table beginning with the next instruction identified by a current instruction pointer of the instruction mapping table before proceeding with another data group.Type: GrantFiled: August 15, 2007Date of Patent: October 7, 2014Assignee: Nvidia CorporationInventors: Michael J. M. Toksvig, Justin M. Mahan, Edward A. Hutchins, Tyson J. Bergland, James T. Battle, Ashok Srinivasan
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Patent number: 8854380Abstract: One embodiment of the present invention sets forth a technique for displaying high-resolution images using multiple graphics processing units (GPUs). The graphics driver is configured to present one virtual display device, simulating a high-resolution mosaic display surface, to the operating system and the application programs. The graphics driver is also configured to partition the display surface amongst the GPUs and transmit commands and data to the local memory associated with the first GPU. A video bridge automatically broadcasts this information to the local memories associated with the remaining GPUs. Each GPU renders and displays only the partition of the display surface assigned to that particular GPU, and the GPUs are synchronized to ensure the continuity of the displayed images. This technique allows the system to display higher resolution images than the system hardware would otherwise support, transparently to the operating system and the application programs.Type: GrantFiled: September 13, 2013Date of Patent: October 7, 2014Assignee: NVIDIA CorporationInventors: Franck R. Diard, Ian M. Williams, Eric Boucher
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Patent number: 8856744Abstract: The HDMI debug cable methods and apparatuses are directed toward a means for pulling up a hot plug detect line to a power line. The debug cable methods and apparatuses also include means for providing an extended display identification data (EDID) code indicating a debug cable or debug host device. The debug cable methods and apparatuses also include means for transmitting and receiving debug commands and data.Type: GrantFiled: August 31, 2011Date of Patent: October 7, 2014Assignee: Nvidia CorporationInventor: Mark Alan Overby
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Publication number: 20140298051Abstract: A feature management system and method of managing access to API functionality. One embodiment of the feature management system includes: (1) a driver configured to carry out functions, including a restricted function, in response to calls thereto, (2) a memory configured to store a management action associated with the restricted function and (3) a feature manager operable to recognize the call to the restricted function and to retrieve the management action from the memory and direct the driver to carry out the management action in addition to the restricted function.Type: ApplicationFiled: March 28, 2013Publication date: October 2, 2014Applicant: Nvidia CorporationInventors: David Wyatt, Daniel Nolan