Abstract: A processing system, a method of carrying out sample-based rendering (such as true or quasi-Monte Carlo rendering) in a multi- or many-core processor processing system and a graphics processing unit (GPU) incorporating the processing system or the method. In one embodiment, the processing system includes: (1) a sample-space distributor operable to distribute a first subset of samples for a pixel of an image to a first compute core for sample-based rendering therewith and a second subset of samples for the pixel to a second compute core for the sample-based rendering therewith, the second subset differing from the first subset and (2) a sample-space combiner associated with the sample-space distributor and operable to combine results of the sample-based rendering.
Type:
Application
Filed:
March 26, 2013
Publication date:
October 2, 2014
Applicant:
Nvidia Corporation
Inventors:
Stefan Radig, Daniel Levesque, Carsten Wächter, Daniel Seibert
Abstract: A system, method, and computer program product for generating mixed video data and three-dimensional data to reduce streaming bandwidth is disclosed. The method includes the steps of receiving graphics data that represents a plurality of graphic objects, selecting a first subset of graphic objects from the plurality of graphic objects to be rendered by a client device, transmitting the first subset of graphic objects to the client device, rendering a second subset of graphic objects from the plurality of graphic objects to generate image data for a frame of video, and transmitting the image data to the client device. The client device is configured to render the first subset of graphic objects to generate additional image data and combine the additional image data with the image data to generate a combined image for display.
Abstract: A system and method for propagating scene information to a renderer. In one embodiment, the system includes: (1) an update request receiver operable to receive an update request from the renderer and determine a point from which the renderer is to be updated and (2) an update propagator associated with the update request receiver and operable to employ a graph containing scene information to construct a change list corresponding to the update request and transmit the change list toward the renderer.
Abstract: A video encoder, a method of encoding a frame of video data, and a three-dimensional modeling system producing an encoded video stream are disclosed herein. In one embodiment, the method includes: (1) receiving from an application a frame of video data to be encoded, (2) determining a gamer's attention area for the frame of video data and (3) changing an encoding of the frame of video data by allocating bits for the frame based upon the gamer's attention area.
Abstract: A system for, and method of, extending useful life of a battery and a battery-powered device incorporating the system or the method. In one embodiment, the system includes: (1) a charge detector operable to detect a charge level contained in the battery, (2) a use modeler coupled to the charge detector and operable to receive data from the charge detector and develop a model of the charge level over time and (3) a charge activator coupled to the use modeler and operable to forego an opportunity to charge the battery when a sufficient charge remains in the battery to last until a full charge can likely be undertaken.
Abstract: A roll compensation system for an electronic device, a method of mitigating impact of an electronic device and an impact-resistant mobile device incorporating the system or the method. In one embodiment, the system includes: (1) a plurality of sensors operable to detect orientation and motion of the electronic device, (2) a controller configured to detect a fall based on the motion and determine a mitigating roll based on the orientation and the motion and (3) a compensator operable to carry out the mitigating roll thereby reducing the probability of a catastrophic impact.
Abstract: A system, method, and computer program product for synchronizing video signals transmitted to a plurality of display devices participating in a spanned desktop environment is disclosed. The method includes the steps of generating an image for display on a spanned desktop environment that includes a plurality of display devices, allocating a portion of the image to each display device in the plurality of display devices, and, for each display device, transmitting a video signal to the display device that represents the portion of the image allocated to that display device. The timing of each video signal is based on a relative position of the display device in a display grid.
Type:
Application
Filed:
March 29, 2013
Publication date:
October 2, 2014
Applicant:
NVIDIA Corporation
Inventors:
Antonio Tejada Lacaci, Martin Schwarzer
Abstract: A computer monitor equalization system includes a computer system having a plurality of monitors and a mobile networking unit that captures display image samples from the plurality of monitors, wherein the display image samples are captured optically for monitor equalization. The computer monitor equalization system also includes an image analyzing unit that analyzes the display image samples to determine a monitor adjustment required to equalize the plurality of monitors. In another aspect, a computer monitor equalization method includes providing a computer system having a plurality of monitors and capturing display image samples from the plurality of monitors, wherein the display image samples are captured optically for monitor equalization employing a mobile network device. The computer monitor equalization method also includes analyzing the display image samples to determine a monitor adjustment required to equalize the plurality of monitors.
Type:
Application
Filed:
March 28, 2013
Publication date:
October 2, 2014
Applicant:
Nvidia Corporation
Inventors:
Andrew Fear, Tom Petersen, Michael McSorley, Gerrit Slavenburg
Abstract: One embodiment sets forth a method for modifying draw calls using a draw-call shader program included in a processing subsystem configured to process draw calls. The draw call shader receives a draw call from a software application, evaluates graphics state information included in the draw call, generates modified graphics state information, and generates a modified draw call that includes the modified graphics state information. Subsequently, the draw-call shader causes the modified draw call to be executed within a graphics processing pipeline. By performing the computations associated with generating the modified draw call on-the-fly within the processing subsystem, the draw-call shader decreases the amount of system memory required to render graphics while increasing the overall processing efficiency of the graphics processing pipeline.
Abstract: Embodiments of the invention may include receiving a design netlist representing a datapath operable to execute a function corresponding to an opcode combination. The datapath may include an input stage, a register stage, and an output stage and the register stage may include a plurality of registers. For a first function corresponding to a first opcode combination, a subset of unused registers in the plurality of registers may be automatically determined. Further, clock gating logic may be automatically inserted into the design netlist, wherein the clock gating logic is operable to dynamically clock gate the subset of unused registers contemporaneously when the datapath executes the first function corresponding to the first opcode combination.
Abstract: A memory circuit in which a level of a first data input appears promptly at an output in response to a clock pulse received. The circuit includes a flip-flop triggered by the clock pulse and configured to receive the first data input and drive a second data input. The circuit also includes a first control input driven by the clock pulse, a second control input driven by the flip-flop and selection logic configured to receive the first and second data inputs and the first and second control inputs. The selection logic is configured to drive the output of the memory circuit to the level of the first data input or of the second data input depending on the first and second control inputs.
Type:
Grant
Filed:
December 15, 2011
Date of Patent:
September 30, 2014
Assignee:
Nvidia Corporation
Inventors:
Venkata Kottapalli, Scott Pitkethly, Christian Klingner, Matthew Gerlach
Abstract: A system, method, and computer program product are provided for hierarchical photon mapping. In use, photons and query locations are generated. Additionally, a bounding volume of the query locations is determined. Further, a set of the photons inside of the bounding volume is determined. It is then determined whether the set of photons and query locations meet predetermined criteria. If it is determined that the set of photons and query locations do not meet the predetermined criteria, the query locations are partitioned, and for each set of the query locations resulting from the partitioning, the above described steps for the hierarchical photon mapping are repeated. Once it is determined that the set of photons and query locations meet the predetermined criteria, a contribution of the set of photons to the query locations is computed.
Type:
Grant
Filed:
October 5, 2011
Date of Patent:
September 30, 2014
Assignee:
NVIDIA Corporation
Inventors:
Alexander Keller, Marc Droske, Leonhard Grunschloss
Abstract: A USB host for wakeup from a sleep state includes a hold memory, a USB host controller, and a USB driver. When going to sleep, the USB driver sends a suspend command to the USB host controller in response to receiving a sleep command. The USB driver also reads a controller context from the USB host controller and saves the controller context in the hold memory. Thereafter, the USB driver turns off one or more supply potentials and one or more clocks in the host controller, and returns a sleep acknowledgement. While in sleep, the interface pins are placed in a hold state and notification to the operating system are disabled.
Abstract: An approach to decoding Huffman symbols in JPEG images is described. One approach involves a method of decoding Huffman codes in a JPEG image file. This method involves obtaining a bitstream sample from a bitstream associated with the JPEG image file. The bitstream sample is compared against a threshold value, to identify a Huffman group number. Information associated with a Huffman group is retrieved, and used to extract the current Huffman symbol from the bitstream. A corresponding symbol value can then be obtained, using the current Huffman symbol and the group information.
Abstract: One embodiment of the present invention sets forth a technique for performing a method for synchronizing divergent executing threads. The method includes receiving a plurality of instructions that includes at least one set-synchronization instruction and at least one instruction that includes a synchronization command, and determining an active mask that indicates which threads in a plurality of threads are active and which threads in the plurality of threads are disabled. For each instruction included in the plurality of instructions, the instruction is transmitted to each of the active threads included in the plurality of threads. If the instruction is a set-synchronization instruction, then a synchronization token, the active mask and the synchronization point is each pushed onto a stack.
Type:
Grant
Filed:
September 28, 2010
Date of Patent:
September 30, 2014
Assignee:
NVIDIA Corporation
Inventors:
Brian Fahs, Ming Y. Siu, Robert Steven Glanville
Abstract: An encoder controller graphics processing unit (GPU) and a method of encoding rendered graphics. One embodiment of the encoder controller GPU includes: (1) an encoder operable to encode rendered frames of a video stream for transmission to a client, and (2) an encoder controller configured to detect a mark embedded in a rendered frame of the video stream and cause the encoder to begin encoding.
Abstract: A quality of service (QoS) management system and a method of forward error correction (FEC). One embodiment of the QoS management system includes a QoS management server including: (1) an encoder operable to forward error correction (FEC) encode a video stream at a current redundancy level for transmission via a network interface controller (NIC), and (2) a processor operable to receive QoS statistics regarding the video stream via the NIC, employ the QoS statistics to determine a new redundancy level and cause the encoder to FEC encode the video stream at the new redundancy level.
Abstract: A system, method, and computer program product for compressing a bounding volume hierarchy is disclosed. The method includes the steps of receiving a bounding volume hierarchy and encoding the bounding volume hierarchy to generate an encoded bounding volume hierarchy, wherein each node in the encoded bounding volume hierarchy indicates whether the node inherits zero or more values from a parent node. The bounding volume hierarchy includes a plurality of nodes, each node in the plurality of nodes is associated with a bounding volume.
Abstract: A quality of service (QoS) management server and a method of managing a streaming bit rate. One embodiment of a QoS management server includes: (1) an encoder operable to encode a video stream at a current bit rate for transmission via a network interface controller (NIC) and (2) a processor operable to receive QoS statistics regarding the video stream via the NIC, employ the QoS statistics to determine a new bit rate and cause the encoder to encode the video stream at the new bit rate.
Abstract: A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer.
Type:
Application
Filed:
March 25, 2013
Publication date:
September 25, 2014
Applicant:
NVIDIA Corporation
Inventors:
John Erik LINDHOLM, Brett W. COON, Stuart F. OBERMAN, Ming Y. SIU, Matthew P. GERLACH