Abstract: A system, method and SPICE model evaluation module executable on a many-core processor. In one embodiment, the module includes: (1) a setup module operable to generate topology matrices T1 and T2, (2) a device evaluation/update module associated with the setup module and operable to generate and update source elements SA for a matrix A and Sb for a right-hand-side vector b and (3) a generation module associated with the device evaluation/update module and operable to generate A using T1 and SA and further generate b using T2 and Sb.

Abstract: A MacBeth color checker chart automatic detection system includes an imaging unit that provides an image and a processing unit that applies an edge detection operation to the image and performs a flood-fill operation on the image to provide a flood-filled image. Additionally, the MacBeth color checker chart automatic detection system includes a testing unit that tests the flood-filled image to provide a modified flood-fill image, wherein a set of heuristic tests are employed to automatically determine quantity and location of MacBeth color checker charts. Generally, the set of heuristic tests are employed to automatically reject regions that are unlikely to belong to a MacBeth color checker chart and to cluster the remaining regions that are likely to belong to a Macbeth color checker chart. A MacBeth color checker chart automatic detection method is also provided.

Abstract: A double-edge-triggered flip-flop circuit and a method for operating the double-edge-trigger flip-flop circuit are provided. Sub-circuits of a flip-flop circuit are coupled to a ground supply and decoupled the sub-circuits from a power supply when a clock signal is asserted. The sub-circuits generate trigger signals including a first pair of signals and a second pair of signals. The first pair of signals is evaluated, levels of the second pair of signals are maintained when the clock signal is asserted, and an output signal is transitioned to equal an input signal based on the trigger signals when the clock signal is asserted.

Abstract: A system, method, and computer program product are provided for adjusting a depth of displayed objects within a region of a display. In use, a display that displays one or more objects three-dimensionally is identified. Additionally, a region within the display is determined. Further, a depth of objects displayed within the region is adjusted.

Abstract: A method for handling error recovery at a user equipment is provided herein. In one embodiment, the method includes: maintaining first and second communication channels between the user equipment and a radio access network; storing a plurality of control messages in a buffer for transmission over the first communication channel; detecting if the first communication channel is disabled; initiating a recovery procedure using the second communication channel that includes restoring the first communication channel using the second communication channel and sending a further message to one of the one or more buffers for transmission on the restored first communication channel; and in response to detecting that the first communication channel is disabled, moderating control messages stored in the one or more buffers.

Abstract: A system, method, and computer program product are provided for reducing noise in an image using depth-based on sweeping over image samples. In use, each noisy pixel of an image having noise is identified. Additionally, for each noisy pixel, at least one sample included in each of a plurality of neighboring pixels to the noisy pixel is identified. Furthermore, the samples are swept over at least partially in a depth-based order to identify a value for the noisy pixel that reduces the noise.

Abstract: A sigma-delta analog-to-digital converter includes an input transconductance stage that provides an analog input current proportional to an analog input voltage and a current summing stage that generates an analog error signal corresponding to a difference between the analog input current and a feedback current. The sigma-delta analog-to-digital converter also includes a forward signal path that processes the analog error signal to provide a digital output signal corresponding to the analog input voltage. Additionally, the sigma-delta analog-to-digital converter includes a feedback path that includes a current steering digital-to-analog converter having both sourcing and sinking current sources, wherein currents provided by the sourcing and sinking current sources are steerable and connected to directly provide the feedback current based on the digital output signal. A sigma-delta analog-to-digital converter operating method is also provided.

Abstract: A system, method, and computer program product are provided for executing processes involving at least one primitive in a graphics processor, utilizing a data structure. In operation, a data structure is associated with at least one primitive. Additionally, a plurality of processes involving the at least one primitive are executed in a graphics processor, utilizing the data structure. Moreover, the plurality of processes include at least one of selecting at least one surface or portion thereof to which to render, or selecting at least one of a plurality of viewports.

Abstract: A system and method are provided for protecting data. In operation, a request to read data from memory is received. Additionally, it is determined whether the data is stored in a predetermined portion of the memory. If it is determined that the data is stored in the predetermined portion of the memory, the data and a protect signal are returned for use in protecting the data. In certain embodiments of the invention, data stored in the predetermined portion of the memory may be further processed and written hack to the predetermined portion of the memory. In other embodiments of the invention, such processing may involve unprotected data stored outside the predetermined portion of the memory.

Abstract: One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.

Abstract: An approach is provided for efficient autostereoscopic support by using a display controller for controlling a display screen of a display system. In one example, the display controller includes the following hardware components: an image receiver configured to receive image data from a source, wherein the image data includes a first image and a second image; a first window controller configured to receive the first image from the image receiver and to scale the first image according to parameters of the display screen in order to generate a scaled first image; a second window controller configured to receive the second image from the image receiver and to scale the second image according to the parameters of the display screen in order to generate a scaled second image; and a blender component configured to interleave the scaled first image with the scaled second image in order to generate a stereoscopic composited image.

Abstract: A system, method, and computer program product are provided for creating a compute construct. In use, a plurality of scripting language statements and a plurality of hardware language statements are identified. Additionally, one or more hardware code components are identified within the plurality of hardware language statements. Additionally, the compute construct is created, utilizing the identified one or more hardware code components and the plurality of scripting language statements.

Abstract: A system, method, and computer program product are provided for multi-sample processing. The multi-sample pixel data is received and an encoding state associated with the multi-sample pixel data is determined. Data for one sample of a multi-sample pixel and the encoding state are provided to a processing unit. The one sample of the multi-sample pixel is processed by the processing unit to generate processed data for the one sample that represents processed multi-sample pixel data for all samples of the multi-sample pixel or two or more samples of the multi-sample pixel.

Abstract: A system, method, and computer program product are provided for creating a hardware design. In use, one or more parameters are received, where at least one of the parameters corresponds to an interface protocol. Additionally, a data flow is constructed based on the one or more parameters. Further, an indication of one or more control constructs is received, where a hardware design is capable of being created, utilizing the constructed data flow and the one or more control constructs.

Abstract: A system, method, and computer program product are provided for multi-sample processing. The multi-sample pixel data is received and is analyzed to identify subsets of samples of a multi-sample pixel that have equal data, such that data for one sample in a subset represents multi-sample pixel data for all samples in the subset. An encoding state is generated that indicates which samples of the multi-sample pixel are included in each one of the subsets.

Abstract: A system, method, and computer program product for automatically extending a lasso region in two-dimensional image editors is disclosed. The method includes the steps of selecting a lasso region of an image based on a path defined by a user using a lasso selection tool, comparing at least a portion of the lasso region to one or more other regions of the image to find a second region that is similar to the lasso region, and extending the selection of the lasso region to include the second region.

Abstract: A jitter buffering system and a method of jitter buffering. The jitter buffering system may be embodied in a quality of service (QoS) management server, including: (1) a network interface controller (NIC) configured to receive one-way-delay statistics regarding a video stream transmitted to a client, and (2) a processer configured to employ the one-way-delay statistics to calculate and recognize jitter and subsequently generate a command for the client to enable jitter buffering.

Abstract: One embodiment of the present invention includes techniques for rasterizing primitives that include edges shared between paths. For each edge, a rasterizer unit selects and applies a sample rule from multiple sample rules. If the edge is shared, then the selected sample rule causes each group of coverage samples associated with a single color sample to be considered as either fully inside or fully outside the edge. Consequently, conflation artifacts caused when the number of coverage samples per pixel exceeds the number of color samples per pixel may be reduced. In prior-art techniques, reducing such conflation artifacts typically involves increasing the number of color samples per pixel to equal the number of coverage samples per pixel. Advantageously, the disclosed techniques enable rendering using algorithms that reduce the ratio of color to coverage samples, thereby decreasing memory consumption and memory bandwidth use, without causing conflation artifacts associated with shared edges.

Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a processor chip, a system functions chip, and an MCM package configured to include the processor chip, the system functions chip, and an interconnect circuit. The processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces manufactured within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The system functions chip is configured to include a second single-ended signaling interface circuit and a host interface. A second set of electrical traces manufactured within the MCM package and configured to couple the host interface to at least one external pin of the MCM package. In one embodiment, each single-, ended signaling interface advantageously implements ground-referenced single-ended signaling.