Abstract: Techniques for selecting a boot display device in the multi-GPU configured computing device include a graphic initialization routine for determining a topology of a plurality of GPUs. It is then determined if a display is coupled to any of the plurality of GPUs. The determination of whether the display is coupled to a GPU is communicated to the other of the plurality of GPUs based upon the determined topology. Thereafter, selection of a given GPU as a primary boot device, by a system initialization routine, is influenced by representing each GPU not coupled to the display as a graphics device and the GPUs coupled to a given display as the primary boot device if one or more displays are coupled to GPUs, and by representing the given GPU as the primary boot device and all other GPUs as graphics devices when the display is not coupled to any of the GPUs.

Abstract: A portable function-expanding device for an electronic device is provided which comprises: a housing with a plurality of accommodating slots provided on an upper surface thereof for accommodating electronic devices respectively, wherein a function-expanding interface is provided in each of the accommodating slots for being connected with a function interface of the electronic device accommodated therein; and a function means located in the housing and connected with the function-expanding interface to fulfill the function-expanding of the corresponding electronic device. The portable function-expanding device for an electronic device fulfills the function-expanding of the corresponding electronic device conveniently. That is, the function-expanding is fulfilled conveniently as required by just inserting the electronic device into the corresponding accommodating slot and connecting the corresponding function-expanding interface in the accommodating with the function interface of the electronic device.

Abstract: Embodiments related to managing potentially invalid results generated/obtained by a microprocessor during runahead are provided. In one example, a method for operating a microprocessor includes causing the microprocessor to enter runahead upon detection of a runahead event. The example method also includes, during runahead, determining that an operation associated with an instruction referencing a storage location would produce a potentially invalid result based on a value of an architectural poison bit associated with the storage location and performing a different operation in response.

Abstract: The present invention provides a turbofan and a graphics card with the turbofan. The turbofan comprises: a turbofan assembly which admits air in an axial direction and dispenses air in a radial direction; an inlet fan assembly disposed at an inlet of the turbofan assembly and disposed coaxially with the turbofan assembly: and a driving means for driving the turbofan assembly and the inlet fan assembly to rotate. The turbofan provided by the invention gathers the ambient air to the inlet through the inlet fan assembly disposed at the inlet of the turbofan assembly, so as to change a negative pressure state at the inlet. Consequently, the cooling efficiency of the turbofan is improved effectively and the noise of the turbofan is reduced.

Abstract: A power source management system of a circuit board that comprises: a processor, comprising a core voltage input terminal; and a core voltage feedback terminal; and a voltage regulating member, comprising a setting terminal with a fixed reference voltage provided thereto; a detecting terminal connected to the core voltage feedback terminal to detect a feedback core voltage from the core voltage feedback terminal; and a core voltage output terminal connected to the core voltage input terminal to provide a core voltage thereto, wherein the core voltage is regulated by the voltage regulating member based on the feedback core voltage, such that the feedback core voltage is equal to the fixed reference voltage, wherein an offset voltage equal to a difference between a desired core voltage of the processor and the fixed reference voltage is provided between the core voltage input terminal and the core voltage feedback terminal by the processor.

Abstract: An approach to reducing interpolation error is described. This approach generally involves using an offset correction table, populated with predetermined offset correction values, to reduce the error introduced by linear interpolation. This approach includes calculating an approximate inverse quantized value. The offset correction table is accessed, and a corrected inverse quantized value is then calculated.

Abstract: A configurable SIMD engine in a video processor for executing video processing operations. The engine includes a SIMD component having a plurality of inputs for receiving input data and a plurality of outputs for providing output data. A plurality of execution units are included in the SIMD component. Each of the execution units comprise a first and a second data path, and are configured for selectively implementing arithmetic operations on a set of low precision or high precision inputs. Each of the execution units have a first configuration and a second configuration, such that the first data path and the second data path are combined to produce a single high precision output in the first configuration, and such that the first data path and the second data path are partitioned to produce a respective first low precision output and second low precision output in the second configuration.

Abstract: Integrated circuit and method for generating a clock signal, the integrated circuit comprising (i) a frequency locked loop comprising a voltage controlled oscillator configured to receive a control input and to generate a clock signal determined by the control input; and (ii) a microprocessor configured to be powered by a supply voltage and to receive the clock signal generated by the voltage controlled oscillator. The integrated circuit is configured to use the supply voltage as the control input, such that the clock signal is determined by the supply voltage.

Abstract: An approach to performing inverse quantization on a quantized integral value is described. This approach involves determining whether a quantized integral value lies within a first range or a second range of possible values. An interpolated inverse quantization value is calculated from the quantized integral value, using a predetermined bit shifting operation, depending on whether the quantized integral value was in the first or the second range.

Abstract: An image processor in an image capture device compensates for the effects of undesirable camera shakes occurring during video capture The image processor receives a pair of source frames representing images of a scene, generates a pair of subsampled frames from the source frames, and computes a coarse displacement of the captured image due to camera shakes by comparing the two subsampled frames. The image processor may then refine the determined coarse displacement by comparing the two source frames and a bound determined by an extent of subsampling, and compensate for the displacement accordingly. Display aberrations such as blank spaces caused due to shifting are also avoided by displaying only a portion of the captured image and shifting the displayed portion to compensate for camera shake. The image processor also recognizes displacements due to intentional camera movement, and does not correct for such displacements.

Abstract: Method, circuitry and device for spreading a clock signal in which the clock signal is received at an input of a variable delay line, the clock signal having been generated by a clock signal generator. In one embodiment, for each edge of the clock signal, the delay introduced by the variable delay line is set in accordance with a stored delay value. For each of a plurality of consecutive edges of the clock signal, the stored delay value is either incremented or decremented based on a randomly generated value for that edge. A spread version of the clock signal is output from the variable delay line, wherein each edge of the spread version of the clock signal is delayed by the respective delay that is set for that edge of the clock signal.

Abstract: A framework for efficient sum of absolute difference (SAD) computations for variable block size, sub-pixel motion estimation is presented. Simultaneous, or parallelized, SAD computations can be performed by storing and re-using previous SAD computational information, which can speed up the performance of a motion estimation module by reducing the number of cycles necessary to perform a particular motion estimation algorithm.

Abstract: Cyclic redundancy check (CRC) values are efficiently calculated using an improved linear feedback shift register (LFSR) circuit. CRC value generation is separated into two sub-calculations, which are then combined to form a final CRC value. A programmable XOR engine performs logic functions via a table lookup rather than via a random logic circuit. LCRC and ECRC calculations are performed using a single shared LFSR circuit. Multiple links share the same CRC value generator. One advantage of the present invention is that CRC values are generated using smaller and fewer LFSR circuits relative to conventional circuit designs. As a result, a CRC value generator utilizing the disclosed techniques consumes less surface area of an integrated circuit and consumes less power, resulting in cooler operation.

Abstract: Methods and system for sharing a hardware resource in a computer system running at least one software process having multiple threads. A lock_indicator is provided in data structures within the computer system. A request is received to use the hardware resource by one of the threads that is defined to be a requesting tread. Based on the lock_indicator, it is determined whether the hardware resource is available for use by the requesting thread. If this indicates that the hardware resource is available, the lock_indicator is set under control of the hardware resource to instead indicate that the hardware resource is unavailable, and a go_indicator signals to indicate that use of the hardware resource for the request can now proceed.

Abstract: A method for rendering a volumetric shadow includes defining a light source ray emanating from a light source, wherein the light source ray intersects a plurality of occluding primitives included within the scene. The method further includes computing an aggregate absorption function for the light source ray, whereby a per-primitive absorption function is computed for each of the plurality of occluding primitives intersecting the light source ray, and the resulting plurality of per-primitive absorption functions are summed to form an aggregate absorption function for the light source ray. A transmittance value is computed as a function of the aggregate absorption function, the transmittance value used to render the volumetric shadow within the scene.

Abstract: A die micro electro-mechanical switch management system and method facilitate power conservation by selectively preventing electrical current from flowing in designated components. A present invention semiconductor die comprises a block of transistors for performing switching operations, a bus (e.g., a power bus, a signal bus, etc.) for conveying electrical current and a micro electro-mechanical switch that couples and decouples the block of transistors to and from the bus. The micro electro-mechanical switch is opened and closed depending upon operations (e.g., switching operations) being performed by the block of transistors. Electrical current is prevented from flowing to the block of transistors when the micro electro-mechanical switch is open and the block of transistors is electrically isolated. The micro electro-mechanical switch can interrupt electrical current flow in a plurality of the bus lines and/or can be included in a relay array.

Abstract: A decoder pipeline may include a decoding (prior to deblocking) stage followed by a deblocking stage. A memory can be coupled to the decoder pipeline. A decoded first macroblock can be output from the decoding stage directly into the deblocking stage, bypassing the memory, if a decoded second macroblock depended on to deblock the first macroblock is already deblocked. Otherwise, the decoded first macroblock is stored in the memory until the second macroblock is deblocked and available to deblock the first macroblock.

Abstract: A technique for reducing artifacts in a digital image, in accordance with one embodiment, includes receiving a stream of raw filter pixel data representing the image. The raw filter pixel data is interpolating to produce red, green-on-red row, green-on-blue row and blue pixel data for each pixel. An artifact in one or more given pixels is reduced as a function of a difference between the green-on-red row and green-on-blue row pixel data of each of the given pixels to generate adjusted interpolated pixel data.

Abstract: A method includes reading, through a processor of a computing device communicatively coupled to a memory, a design of an electronic circuit at a first level higher than a second level at which design verification and/or design simulation of the electronic circuit is to be conducted, and representing instances of elements of the electronic circuit in a data structure. The method also includes parsing, at the first level, the design to automatically generate a list of regular expressions related to text-matching strings with the elements of the electronic circuit based on removing undesired instances related to the elements from the data structure, and pruning, at the second level, connectivity descriptors of the electronic circuit based on the automatically generated list of regular expressions. Further, the method includes optimizing the design verification and/or the design simulation at the second level based on the pruned connectivity descriptors thereof.

Abstract: Under some conditions, requests transmitted between different devices in a computing system may be blocked in a way that prevents the request from being processed, resulting in a deadlock condition. A skid buffer is used to allow additional requests to be queued in order to remove the blockage and end the deadlock condition. Once the deadlock condition is removed, the requests are processed and the additional buffer entries in the skid buffer are disabled.