Abstract: One embodiment of the present invention sets forth a technique providing an optimized way to allocate and access memory across a plurality of thread/data lanes. Specifically, the device driver receives an instruction targeted to a memory set up as an array of structures of arrays. The device driver computes an address within the memory using information about the number of thread/data lanes and parameters from the instruction itself. The result is a memory allocation and access approach where the device driver properly computes the target address in the memory. Advantageously, processing efficiency is improved where memory in a parallel processing subsystem is internally stored and accessed as an array of structures of arrays, proportional to the SIMT/SIMD group width (the number of threads or lanes per execution group).

Abstract: A system and method for correcting image data. Embodiments of the present invention provide calibration and image correction to overcome various lens effects including lens shading and lens imperfections. In one embodiment, the correction of image data is performed via utilization of a spline surface (e.g., Bezier surface). The use of spline surfaces facilitates efficient hardware implementation. The image correction may be performed on a per channel and illumination type basis. In another embodiment, the present invention provides a method for determine a spline surface to be used for calibrating an image signal processor to be used in correcting image data.

Abstract: A method of storing content, in accordance with one embodiment of the present invention, includes receiving an item of content in a protected format and a key corresponding to the item of content. The item of content in its protected format may be stored on a mass storage device. The key may also be stored in a safeguarded format on the mass storage device.

Abstract: A synchronous sequential latch array generated by an automated system for generating master-slave latch structures is disclosed. A master-slave latch structure includes N/2 rows of master-slave latch pairs, an N/2-to-1 multiplexer and control logic. N is equal to the number of latches that are included in the latch array.

Abstract: A method, computer program product, and system are provided for multi-threaded video encoding. The method includes the steps of generating a set of motion vectors in a hardware video encoder based on a current frame of a video stream and a reference frame of the video stream, dividing the current frame into a number of slices, encoding each slice of the current frame based on the set of motion vectors, and combining the encoded slices to generate an encoded bitstream.

Abstract: Embodiments of the present invention include devices having multiple dies packaged together in the same package. The multiple dies are disposed on an interposer which is then disposed on a package substrate. The interposer includes a semiconductor substrate, such as silicon, having vias extending from a front surface of the interposer to a back surface of the interposer. The interposer may be a passive interposer or an active poser. An active interposer includes the functionality of one or more dies and thus reduces the number of dies disposed on the active interposer.

Abstract: A camera tuning engine within a digital camera includes a machine learning engine that generates a configuration file for the digital camera based on raw images captured by the digital camera. The digital camera implements a set of rendering algorithms that render trial images from the raw images based on parameters included in the configuration file. A training engine within the camera tuning engine then compares the trial images to target images provided from an external source. Based on differences between the trial images and the target images, the training engine adjusts weight values within the machine learning engine. By performing this process iteratively, the training engine trains the machine learning engine to generate a configuration file that may be used by the digital camera to render images that are similar to the target images.

Abstract: Methods for code protection are disclosed. A method includes using a security processing component to access an encrypted portion of an application program that is encrypted by an on-line server, after a license for use of the application program is authenticated by the on-line server. The security processing component is used to decrypt the encrypted portion of the application program using an encryption key that is stored in the security processing component. The decrypted portion of the application program is executed based on stored state data. Results are provided to the application program that is executing on a second processing component.

Abstract: One embodiment of the present invention sets forth a technique for rendering graphics primitives in parallel while maintaining the API primitive ordering. Multiple, independent geometry units perform geometry processing concurrently on different graphics primitives. A primitive distribution scheme delivers primitives concurrently to multiple rasterizers at rates of multiple primitives per clock while maintaining the primitive ordering for each pixel. The multiple, independent rasterizer units perform rasterization concurrently on one or more graphics primitives, enabling the rendering of multiple primitives per system clock.

Abstract: A method for automatically generating master-slave latch structures is disclosed. A method includes, from another logic synthesis system that invokes a logic synthesis system for generating master-slave latch structures, accessing high level design descriptions of a master-slave latch structure that indicate a fully registered flow control structure design and based on the high level design descriptions, generating a master-slave latch structure design to include at least one master-slave latch pair.

Abstract: Embodiments of the present technology are directed toward circuits for gating pre-charging sense nodes within a flip-flop when an input data signal changes and a clock signal is in a given state. Embodiments of the present technology are further directed toward circuits for maintaining a state of the sense nodes.

Abstract: Testing operation of processors setup to operate in different modes. In an embodiment, each tester system includes a processor setup to operate in a corresponding mode. A user sends a test request to a scheduler system indicating the mode of the processor sought to be tested, and the scheduler system forwards the test request to one of the tester systems with a processor setup to test the requested configuration. The scheduler system may maintain configuration information indicating which processors are setup to test which modes of interest, and also status information indicating which tester systems are presently available for testing. The configuration information and status information is used in determining a specific suitable tester system to which a test request is to be forwarded.

Abstract: A method and apparatus for supporting a self-refreshing display device coupled to a graphics controller are disclosed. A technique for setting the operating state of the graphics controller during initialization from a deep sleep state is described. The graphics controller may set the operating state based on a signal that controls whether the graphics controller executes a warm-boot initialization procedure or a cold-boot initialization procedure. In the warm-boot initialization procedure, instructions and values stored in a non-volatile memory connected to the graphics controller may be used to set the operating state of the graphics controller. In one embodiment, the graphics controller may determine whether any changes have been made to the physical configuration of the computer system and, if the physical configuration has changed, the graphics controller may set the operating state based on values received from a software driver.

Abstract: A present invention pixel processing system and method permit complicated three dimensional images to be rendered with shallow graphics pipelines including reduced gate counts and facilitates power conservation by utilizing a single unified data fetch stage (e.g., unified data fetch module) that retrieves a variety of different pixel surface attribute values (e.g., depth, color, and/or texture values) in a single stage. Different types of pixel surface attribute data (e.g., depth, color, texture) associated with multiple graphics processing functions (e.g., color blending, texture mapping, etc.) are retrieved in the single unified data fetch graphics pipeline stage. The pixel surface attribute values may be placed in corresponding variable fields of a pixel packet row. The pixel packet rows including the pixel surface attribute values are forwarded to downstream graphics pipeline stages (e.g., an arithmetic logic pipestage).

Abstract: Embodiments of the present invention include a host computer system implemented method comprising receiving an indication of total requested display size of a remotely coupled client computer system. The method further includes automatically determining a number of display screens and a predetermined average display screen size. The method further includes an operating system of the host computer system allocating therein a display area to accommodate the total requested display size and dividing the display area into a number of separate portions equal to the number of display screens usable by the client computer system. The method further includes allocating each separate portion of the display area of the host computer system to a respective display screen of the client computer wherein each separate portion so allocated functions as a separate and independent display screen.

Abstract: A method and a system are provided for speculative periodic synchronization. A phase value representing a measured phase of the second clock signal relative to the first clock signal measured at least one cycle earlier is received. A period value representing a period of the second clock signal relative to the first clock signal measured at least one cycle earlier is also received. A reduced timing margin is determined based on the phase value and the period value. A speculatively synchronized output signal is generated based on the reduced timing margin.

Abstract: Prefetching is permitted to cross from one physical memory page to another. More specifically, if a stream of access requests contains virtual addresses that map to more than one physical memory page, then prefetching can continue from a first physical memory page to a second physical memory page. The prefetching advantageously continues to the second physical memory page based on the confidence level and prefetch distance established while the first physical memory page was the target of the access requests.

Abstract: A technique for enhancing the efficiency and speed of data transmission within and across multiple, separate computer systems includes the use of an MPI library/engine. The MPI library/engine is configured to facilitate the transfer of data directly from one location to another location within the same computer system and/or on separate computer systems via a network connection. Data stored in one GPU buffer may be transferred directly to another GPU buffer without having to move the data into and out of system memory or other intermediate send and receive buffers.

Abstract: A technique for enhancing the efficiency and speed of data transmission within and across multiple, separate computer systems includes the use of an MPI library/engine. The MPI library/engine is configured to facilitate the transfer of data directly from one location to another location within the same computer system and/or on separate computer systems via a network connection. Data stored in one GPU buffer may be transferred directly to another GPU buffer without having to move the data into and out of system memory or other intermediate send and receive buffers.

Abstract: A method of entering a power conservation state comprises selecting and entering one of a plurality of low power states for the computer system in response to a detected system idle event. The plurality of low power states comprise a first low power state and a second low power state for the computer system. A memory of the computer system is self refreshed during the first low power state. A baseband module of the computer system remains powered, and the memory is accessible to the baseband module during the second low power state. The one low power state is selected depending upon baseband module activity. The method also includes exiting from the one of a plurality of low power states when a wake event is detected.