Abstract: Cyclic redundancy check (CRC) values are efficiently calculated using an improved linear feedback shift register (LFSR) circuit. CRC value generation is separated into two sub-calculations, which are then combined to form a final CRC value. A programmable XOR engine performs logic functions via a table lookup rather than via a random logic circuit. LCRC and ECRC calculations are performed using a single shared LFSR circuit. Multiple links share the same CRC value generator. One advantage of the present invention is that CRC values are generated using smaller and fewer LFSR circuits relative to conventional circuit designs. As a result, a CRC value generator utilizing the disclosed techniques consumes less surface area of an integrated circuit and consumes less power, resulting in cooler operation.

Abstract: A system and method are provided for inserting synchronization statements into a program file to mitigate race conditions. The method includes reading a program file and determining one or more convergent statements in the program file. The method also includes inserting one or more synchronization statements in the program file between the determined convergent statements. The method further includes removing one or more of the inserted synchronization statements and writing the modified program file. The method may include, after removing the inserted synchronization statements, identifying to a user any remaining inserted synchronization statements.

Abstract: A system and method are provided for test program generation using key enumeration and string replacement. A system includes a test program generator and a tester. The tester receives a test program from the test program generator and tests one or more products according to the test program. The test program generator receives a seed file from a seed file database and a configuration file from a configuration file database. The test program generator iterates over enumeration keys in the configuration file and, for each key, apply to the seed file one or more rules in the configuration file keyed to the enumeration key. Applying a rule includes replacing in the seed file one or more occurrences of a predicate value of the rule with a transformation value of the rule. The test program generator also outputs to the tester the modified first seed file as the test program.

Abstract: A system and method for transmitting state based input over a network are presented. Embodiments of the present invention are operable to generate vector data comprising a composite of all state data associated with the state of all user input claims of a client system and transmit the vector data from the client device to a host device over a network. Embodiments of the present invention are further operable at the host device to determine a simulated input state at the client side by performing a comparison of the vector data currently received to a last known vector data and rendering output in response to the comparison.

Abstract: An integrated circuit (IC) is designed that includes one variant having a plurality of a modular circuits communicatively coupled together and a second variant having a sub-set of the plurality of modular circuits. The modular circuits are then laid out on a wafer for fabricating each of the variants of the IC. The layout includes routing communicative couplings between the sub-set of the modular circuits of the second variant to the other modular circuits of the first variant in one or more metallization layers to be fabricated last. Fabricating the IC is then started, up to but not including the one or more metallization layers to be fabricated last. One or more of the plurality of variants of the IC is selected based upon a demand predicted during fabrication. Fabrication then continues with the last metallization layers of the IC according to the selected layout.

Abstract: A partition unit that includes a cache for storing both data and error-correcting code (ECC) checkbits associated with the data is disclosed. When a read command corresponding to particular data stored in a memory unit results in a cache miss, the partition unit transmits a read request to the memory unit to fetch the data and store the data in the cache. The partition unit checks the cache to determine if ECC checkbits associated with the data are stored in the cache and, if the ECC checkbits are not in the cache, the partition unit transmits a read request to the memory unit to fetch the ECC checkbits and store the ECC checkbits in the cache. The ECC checkbits and the data may then be compared to determine the reliability of the data using an error-correcting scheme such as SEC-DED (i.e., single error-correcting, double error-detecting).

Abstract: One embodiment of the present invention sets forth an integrated circuit package including a substrate, an integrated circuit die, and a plurality of solder bump structures. The substrate includes a first plurality of interconnects disposed on a first surface of the substrate. The integrated circuit die includes a second plurality of interconnects disposed on a first surface of the integrated circuit die. The plurality of solder bump structures couple the first plurality of interconnects to the second plurality of interconnects. The first plurality of interconnects are configured to be substantially aligned with the second plurality of interconnects when the integrated circuit package is at a first temperature within a range of about 0° C. to about ?100° C. The first plurality of interconnects are configured to be offset from the second plurality of interconnects when the integrated circuit package is at a temperature above the first temperature.

Abstract: A circuit for multiplying a digital signal by a variable gain, controlled in dependence on a digital gain control value. The circuit comprises: a multiplier input for receiving the digital signal; a multiplier output for outputting the digital signal multiplied by the gain; a plurality of multiplier stages each arranged to multiply by a respective predetermined multiplication factor; and switching circuitry arranged so as to apply selected ones of the multiplier stages in a multiplication path between the input and output, in dependence on the digital gain control value. The multiplication factors are arranged such that binary steps in the digital gain control value result in logarithmic steps in said gain.

Abstract: One embodiment of the present invention sets forth an integrated circuit package including a substrate, an integrated circuit die, a first plurality of solder bump structures, and a first plurality of variable-size solder bump structures. The first plurality of solder bump structures electrically couple the integrated circuit die to the substrate. The first plurality of variable-size solder bump structures are disposed on a bottom surface of the substrate. The first plurality of variable-size solder bump structures are sized to be substantially coplanar with a seating plane of the integrated circuit package.

Abstract: A system and method for network driven automatic adaptive rendering impedance are presented. Embodiments of the present invention are operable to dynamically throttle the frame rate associated with an application using a server based graphics processor based on determined communication network conditions between a server based application and a remote server. Embodiments of the present invention are operable to monitor network conditions between the server and the client using a network monitoring module and correspondingly adjust the frame rate for a graphics processor used by an application through the use of a throttling signal in response to the determined network conditions. By throttling the application in the manner described by embodiments of the present invention, power resources of the server may be conserved, computational efficiency of the server may be promoted and user density of the server may be increased.

Abstract: One embodiment of the present invention sets forth a processing module including an interposer and a plurality of processing nodes. The interposer includes a plurality of through substrate vias. Each processing node includes a processing unit die coupled directly to a top surface of the interposer with a first plurality of solder bump structures, a memory die coupled directly to the top surface of the interposer with a second plurality of solder bump structures, and a plurality of circuit elements electrically coupling the processing unit die and the memory die. The processing module further includes a plurality of electrical connections formed on a bottom surface of the interposer and electrically coupled to the plurality of processing nodes through the plurality of through substrate vias. The processing module further comprises a plurality of interconnecting circuit elements electrically interconnecting the plurality of processing nodes.

Abstract: A static read-only memory (SRAM) includes one or more bit cell rows that each includes a collection of bit cells. Each bit cell row is coupled to two or more different wordlines, where each wordline associated with a given bit cell row provides memory access to a different subset of bit cells within that bit cell row.

Abstract: A method and a system are provided for variation-tolerant synchronization. A phase value representing a phase of a second clock signal relative to a first clock signal and a period value representing a relative period between the second clock signal and the first clock signal are received. An extrapolated phase value of the second clock signal relative to the first clock signal corresponding to a next transition of the first clock signal is computed based on the phase value and the period value.

Abstract: An approach is provided for enabling power reduction in floating-point operations. In one example, a system receives floating-point numbers of a fused multiply-add instruction. The system determines the fused multiply-add instruction does not require compliance with a standard of precision for floating-point numbers. The system generates gating signals for an integrated circuit that is configured to perform operations of the fused multiply-add instruction. The system then sends the gating signals to the integrated circuit to turn off a plurality of logic gates included in the integrated circuit.

Abstract: One aspect provides a semiconductor device. The semiconductor device, in this embodiment, includes a semiconductor substrate having a lower surface and an upper surface, as well as a heat-spreading lid configured to attach to the upper surface of the semiconductor substrate. In this embodiment, at least one of the semiconductor substrate or the heat-spreading lid has a plurality of openings extending entirely there through. The semiconductor device, in accordance with this aspect, further includes a plurality of fasteners operable to extend through the plurality of openings and engage the other of the semiconductor substrate or the heat-spreading lid to attach the semiconductor substrate and the heat-spreading lid.

Abstract: A method and a system are provided for clock phase detection. A first set of delayed versions of a first clock signal is generated and a second set of delayed versions of a second clock signal is generated. The second set of delayed versions of the second clock signal is sampled using the first set of delayed versions of the first clock signal to produce an array of clock samples in a domain corresponding to the first clock signal. At least one edge indication is located within the array of clock samples.

Abstract: A system, method and computer program product are provided for bump mapping in a hardware graphics processor. Initially, a first set of texture coordinates is received. The texture coordinates are then multiplied by a matrix to generate results. A second set of texture coordinates is then offset utilizing the results. The offset second set of texture coordinates is then mapped to color.

Abstract: One embodiment of the present invention sets forth a technique for decomposing and filling cubic Bèzier segments of paths without tessellating the paths. Path rendering may be accelerated when a GPU or other processor is configured to perform the decomposition operations. Cubic Bèzier paths are classified and decomposed into simple cubic Bèzier path segments based on the classification. A stencil buffer is then generated that indicates pixels that are inside of the decomposed cubic Bèzier segments. The paths are then filled according to the stencil buffer to produce a filled path.

Abstract: An operating system providing multi-touch support for (user) applications in a mobile device. In one embodiment, a check of whether the touch screen (in the mobile device) has multi-touch capability is performed. A first interface with multi-touch capability is provided to the (user) applications if the touch screen has multi-touch capability and a second interface with single touch capability being provided if the touch screen does not have multi-touch capability. The first and second interfaces may be provided by corresponding device drivers loaded when the mobile device is initialized with the operating system. A device driver (providing the second interface) is also designed to perform the check and execute another device driver (providing the first interface) if the touch screen has multi-touch capability.

Abstract: A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. A crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.