Abstract: A system, method, and computer program product are provided for rendering pixels with multiple semi-transparent surfaces. In use, a pixel is identified. Additionally, an operation to generate a plurality of samples for the pixel is performed. Further, a subset of the samples for each of at least one semi-transparent surface associated with the pixel is selected at least in part in a random manner. Moreover, the pixel is rendered utilizing the selected subset of the samples for each of the at least one semi-transparent surface.

Abstract: One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a latch circuit that presents a low number of loads to the clock signal. The clock is only coupled to a bridging transistor and a pair of clock-activated pull-down or pull-up transistors. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled by the bridging transistor and a propagation sub-circuit is activated and deactivated by the pair of clock-activated transistors.

Abstract: A method, device and computer program product is provided for sending a data signal and a clock signal between a radio frequency circuit of a device and a baseband circuit of the device, the radio frequency circuit being configured for at least one of transmission and reception of radio signals in a radio frequency band, where the clock signal has a clock frequency Fc. The method comprises selecting the clock frequency Fc to be a rational multiple of the 0.270833 MHz symbol rate of the Global System for Mobile Communications (GSM) standard and a rational multiple of the 3.84 MHz chipping rate of the Wideband Code Division Multiple Access (WCDMA) interface. The clock frequency Fc is selected such that the clock signal can be generated using a 38.4 MHz or 19.2 MHz reference clock signal, a non-fractional Phase Locked Loop clock multiplier and an output divider, without first having to divide down the reference clock signal.

Abstract: The present invention discloses a method and a device for providing a game. The method includes: a detection step, for determining an additional display device being attached to a mobile device; and a push step, for pushing multimedia information of the game to the additional display device to be presented by the additional display device, and pushing a visual human machine interface of the game to a display of the mobile device to be displayed by the display; wherein, a controlled object displayed on the additional display device is controlled by the visual human machine interface. The above-mentioned method and device for providing a game can make a game machine have a smaller size and be more portable, display multimedia information of a game on a bigger screen for players and provide players with a visual human machine interface on the entire screen of a mobile device, and therefore it improves user experiences.

Abstract: A system and method for power management by performing clock-gating at a clock source. In the method a critical stall condition is detected within a clocked component of a core of a processing unit. The core includes one or more clocked components synchronized in operation by a clock signal distributed by a clock grid. The clock grid is clock-gated to suspend distribution of the clock signal to the core during the critical stall condition.

Abstract: A method of controlling data transmission over a radio network between a first machine-type communication (MTC) entity and a second MTC entity in a wireless telecommunications system is described. The method comprises an element of the radio network architecture, for example a base station, deriving a transmission cost for transmitting data between the first and second MTC entities based on traffic load, and then communicating the transmission cost to one or both of the MTC entities. The MTC entities may then control their data transmissions based on the transmission cost. Thus the radio network is able to dynamically manage traffic load by providing a cost incentive for transmitting MTC data when network resources are under utilised and applying a cost penalty for transmissions made while the network is relatively busy. Furthermore, the MTC entities of the wireless communication system are able to select times and/or manner of data transmissions to reduce their overall cost of using the network.

Abstract: The present invention discloses a naked eye 3D video system for backing a vehicle and vehicles including the system. The naked eye 3D video system includes: two cameras for being installed on the rear of the vehicle and configured to capture images of the scene behind the vehicle respectively; a processor configured to divide the images captured by the two cameras into image strips in equidistance respectively, and integrate alternatively the divided image strips together into a integrated image in the manner of interleave; and a display device for being installed on the instrument panel of the vehicle, and configured to display the integrated image in the form of three dimensions for a driver to watch with the naked eye. The above naked eye 3D video system for backing a vehicle provided by the present invention can make the driver see clearly any obstacle in the scene behind the vehicle and understand spatial distribution information between the vehicle and the obstacle.

Abstract: A processing system includes a microprocessor, a hardware decoder arranged within the microprocessor, and a translator operatively coupled to the microprocessor. The hardware decoder is configured to decode instruction code non-native to the microprocessor for execution in the microprocessor. The translator is configured to form a translation of the instruction code in an instruction set native to the microprocessor and to connect a branch instruction in the translation to a chaining stub. The chaining stub is configured to selectively cause additional instruction code at a target address of the branch instruction to be received in the hardware decoder without causing the processing system to search for a translation of additional instruction code at the target address.

Abstract: A system, method, and computer program product are provided for managing miss requests. In use, a miss request is received at a unified miss handler from one of a plurality of distributed local caches. Additionally, the miss request is managed, utilizing the unified miss handler.

Abstract: An input/output unit for a computer system that is interfaced with a memory unit having a plurality of partitions manages completions of read requests in the order that they were made. A read request buffer tracks the order in which the read requests were made so that read data responsive to the read requests can be completed and returned to a requesting client in the order the read requests were made.

Abstract: A method for executing an application program using streams. A device driver receives a first command within an application program and parses the first command to identify a first stream token that is associated with a first stream. The device driver checks a memory location associated with the first stream for a first semaphore, and determines whether the first semaphore has been released. Once the first semaphore has been released, a second command within the application program is executed. Advantageously, embodiments of the invention provide a technique for developers to take advantage of the parallel execution capabilities of a GPU.

Abstract: One or more embodiments of the invention set forth techniques to perform integer division using a floating point hardware unit supporting floating point variables of a certain bit size. The numerator and denominator are integers having a bit size that is greater than the bit size of the floating point variables supported by the floating point hardware unit. Error correcting techniques are utilized to account for any loss of precision caused by the floating point operations.

Abstract: One embodiment of the invention sets forth a mechanism to transmit commands received from an L2 cache to a bank page within the DRAM. An arbiter unit determines which commands from a command sorter to transmit to a command queue. An activate command associated with the bank page related to the commands is also transmitted to an activate queue. The last command in the command queue is marked as “last.” An interlock counter stores a count of “last” commands in the read/write command queue. A DRAM controller transmits activate and commands from the activate queue and the command queue to the DRAM. Each time a command marked as “last” is encountered, the DRAM controller decrements the interlock counter. If the count in the interlock counter is zero, then the command marked as “last” is marked as “auto-precharge.” The “auto-precharge” command, when processed, causes the bank page to be closed.

Abstract: A heat transfer apparatus and method are provided for transferring heat between integrated circuits. In use, a heat transfer medium is provided with a first end in thermal communication with a first integrated circuit and a second end in thermal communication with a second integrated circuit. Furthermore, a single casting formed about the heat transfer medium and defining at least one heat sink is provided for thermal communication with the first integrated circuit or the second integrated circuit.

Abstract: A display refresh system, method and computer program product are provided. In use, at least one aspect of a display of content is identified by monitoring commands. Based on such identified aspect(s), a refresh rate of a display utilized for the display of the content may be adjusted.

Abstract: One embodiment of the present invention sets forth a technique for efficiently creating and accessing an A-Buffer that supports multi-sample compression techniques. The A-Buffer is organized in stacks of uniformly-sized tiles, wherein the tile size is selected to facilitate compression techniques. Each stack represents the samples included in a group of pixels. Each tile within a stack represents the set of sample data at a specific per-sample rendering order index that are associated with the group of pixels represented by the stack. Advantageously, each tile includes tile compression bits that enable the tile to maintain data using existing compression formats. As the A-Buffer is created, a corresponding stack compression buffer is also created. For each stack, the stack compression buffer includes a bit that indicates whether all of the tiles in the stack are similarly compressed and, consequently, whether the GPU may operate on the stack at an efficient per pixel granularity.

Abstract: A system and method for preconditioning or smoothing (e.g., multi-color DILU preconditioning) for iterative solving of a system of equations. The method includes accessing a matrix comprising a plurality of coefficients of a system of equations and accessing coloring information corresponding to the matrix. The method further includes determining a diagonal matrix based on the matrix and the coloring information corresponding to the matrix. The determining of the diagonal matrix may be determined in parallel on a per color basis. The method may further include determining an updated solution to the system of equations where the updated solution is determined in parallel on a per color basis using the diagonal matrix.

Abstract: One embodiment of the present invention sets forth a mechanism for transmitting and receiving ground-referenced single-ended signals. A transmitter combines a direct current (DC) to DC converter including a flying capacitor with a 2:1 clocked multiplexer to drive a single-ended signaling line. The transmitter drives a pair of voltages that are symmetric about the ground power supply level. Signaling currents are returned to the ground plane to minimize the generation of noise that is a source of crosstalk between different signaling lines. Noise introduced through the power supply is correlated with the switching rate of the data and may be reduced using an equalizer circuit.

Abstract: A 3D display system and a 3D displaying method are provided in the present invention. The 3D display system comprising: a display device; a detecting device, for detecting a viewing position of a viewer; and a control device, for controlling a video frame to be converted onto a virtual plane perpendicular to visual line of the viewing position according to the viewing position, and mapping converted video frame onto the display device to display a 3D image on the display device. The 3D display system provided by the present invention adjusts the virtual plane, onto which the video frame is converted, by detecting the viewing position of the viewer, such that the 3D image displayed on the display device can be adjusted according to the viewing position of the viewer. It causes that the viewer can view the 3D image having no deflection, without being limited by the viewing position.

Abstract: A system and method for implementing memory overlays for portable pointer variables. The method includes providing a program executable by a heterogeneous processing system comprising a plurality of a processors running a plurality of instruction set architectures (ISAs). The method also includes providing a plurality of processor specific functions associated with a function pointer in the program. The method includes executing the program by a first processor. The method includes dereferencing the function pointer by mapping the function pointer to a corresponding processor specific feature based on which processor in the plurality of processors is executing the program.