Abstract: Described herein are a number of approaches for implementing a multistandard video encoder. In several embodiments, a single encoder supports multiple video encoding standards via dedicated hardware datapaths, while using shared buffers to store a video data between processing stages. In one such embodiment, system for video encoding is described. The system includes a number of encoding stages, for performing tasks associated with encoded video data. The system also includes a number of encoding buffers, coupled to the encoding stages, for storing video data between encoding stages. The encoding stages are operable to encode the video data in accordance with a number of video encoding standards, and the encoding buffers are operable to store partially encoded video data, regardless of the video encoding standard selected.

Abstract: Systems and methods for texture processing are presented. In one embodiment a texture method includes creating a sparse texture residency translation map; performing a probe process utilizing the sparse texture residency translation map information to return a finest LOD that contains the texels for a texture lookup operation; and performing the texture lookup operation utilizing the finest LOD. In one exemplary implementation, the finest LOD is utilized as a minimum LOD clamp during the texture lookup operation. A finest LOD number indicates a minimum resident LOD and a sparse texture residency translation map includes one finest LOD number per tile of a sparse texture. The sparse texture residency translation can indicate a minimum resident LOD.

Abstract: One or more client engines issues write transactions to system memory or peer parallel processor (PP) memory across a peripheral component interconnect express (PCIe) interface. The client engines may issue write transactions faster than the PCIe interface can transport those transactions, causing write transactions to accumulate within the PCIe interface. To prevent the accumulation of write transactions within the PCIe interface, an arbiter throttles write transactions received from the client engines based on the number of write transactions currently being transported across the PCIe interface.

Abstract: A storage controller which uses the same buffer to store data elements retrieved from different secondary storage units. In an embodiment, the controller retrieves location descriptors ahead of when data is available for storing in a target memory. Each location descriptor indicates the memory locations at which data received from a secondary storage is to be stored. Only a subset of the location descriptors may be retrieved and stored ahead when processing each request. Due to such retrieval and storing of limited number of location descriptors, the size of a buffer used by the storage controller may be reduced. Due to retrieval of the location descriptors ahead, unneeded buffering of the data elements within the storage controller is avoided, reducing the latency in writing the data into the main memory, thus improving performance.

Abstract: Embodiments of the invention may include receiving a design netlist representing a datapath operable to execute a function corresponding to an opcode combination. The datapath may include an input stage, a register stage, and an output stage and the register stage may include a plurality of registers. For a first function corresponding to a first opcode combination, a subset of unused registers in the plurality of registers may be automatically determined. Further, clock gating logic may be automatically inserted into the design netlist, wherein the clock gating logic is operable to dynamically clock gate the subset of unused registers contemporaneously when the datapath executes the first function corresponding to the first opcode combination.

Abstract: Rendered image data is encoded by a server computing device and transmitted to a remote client device that executes an interactive application program. The client device decodes and displays the image data and, when the user interacts with the application program, the client device provides input control signals to the server computing device. When input control signals are received by the server, the latency incurred for encoding and/or decoding the image data is reduced. Therefore, the user does not experience inconsistencies in the frame rate of images displayed on the client when the user interacts with the application program. The reduction in latency is achieved by dynamically switching from a hardware implemented encoding technique to a software implemented encoding technique. Latency may also be reduced by dynamically switching from a hardware implemented decoding technique to a software implemented decoding technique.

Abstract: In a processor, a method for speculative permission acquisition for access to a shared memory. The method includes receiving a store from a processor core to modify a shared cache line, and in response to receiving the store, marking the cache line as speculative. The cache line is then modified in accordance with the store. Upon receiving a modification permission, the modified cache line is subsequently committed.

Abstract: A number of images of a scene are captured and stored. The images are captured over a range of values for an attribute (e.g., a camera setting). One of the images is displayed. A location of interest in the displayed image is identified. Regions that correspond to the location of interest are identified in each of the images. Those regions are evaluated to identify which of the regions is rated highest with respect to the attribute relative to the other regions. The image that includes the highest-rated region is then displayed.

Abstract: A communication system is described providing for access to registers over a control register access bus. The system includes one or more core units including one or more addressable core registers, wherein the units are coupled to the communication bus. The system also includes one or more core clusters (CCLUSTERs) coupled to the one or more core units through the communication bus. The CCLUSTERs provide one or more gateways for transactions to and from the one or more core units. The system also includes a request ordering and coherency (ROC) unit coupled to the CCLUSTERs through the communication bus that is configured for scheduling transactions relating to the registers onto the communication bus. The system also includes the one or more addressable registers that are located in the ROC unit, the CCLUSTERs, and the one or more core units.

Abstract: One embodiment of the present invention sets forth a technique for displaying high-resolution images using multiple graphics processing units (GPUs). The graphics driver is configured to present one virtual display device, simulating a high-resolution mosaic display surface, to the operating system and the application programs. The graphics driver is also configured to partition the display surface amongst the GPUs and transmit commands and data to the local memory associated with the first GPU. A video bridge automatically broadcasts this information to the local memories associated with the remaining GPUs. Each GPU renders and displays only the partition of the display surface assigned to that particular GPU, and the GPUs are synchronized to ensure the continuity of the displayed images. This technique allows the system to display higher resolution images than the system hardware would otherwise support, transparently to the operating system and the application programs.

Abstract: An equalization parameter analyzer includes a parameter section configured to acquire at least one current parameter for a wireless receiver and an analyzer section configured to compare the at least one current parameter with at least one corresponding previous parameter. Additionally, the equalization parameter analyzer also includes a coefficients section configured to initiate a generation of new equalizer coefficients in the wireless receiver based on a change between the at least one current and corresponding previous parameters that exceeds a predefined threshold. A method of equalization coefficients generation is also provided.

Abstract: Memory access techniques, in accordance with embodiments of the present technology, redirect memory access requests received from a baseband processor to shared memory coupled to an application processor. The techniques enable substantially real time read and write accesses by the application and baseband processors to the shared memory coupled to the application processor.

Abstract: Pictures can be taken with multiple (e.g., two) cameras, and the statistics associated with any of those pictures can be used to correct (e.g., color balance) any of the other pictures. Generally speaking, first image data captured by a first camera is accessed (e.g., retrieved from memory). Similarly, second image data captured by a second camera is accessed. The first image data and second image data are acquired at or about the same time using the first and second cameras together (e.g., at the same location, so that each camera is subject to the same light source). The first image data can then be processed (e.g., color balanced) using information that is derived using the second image data.

Abstract: A method of video reconstruction includes providing a hardware accelerator to a video processing component of a video processing system, and a driver for the video processing component. In addition, the method includes segmenting macroblocks of a destination video frame in a raster order into groups based on reference parameters thereof using the driver, where the reference parameters define compensation needs of macroblocks of the destination frame. The method also includes constructing an indexed array of linked-lists using the driver, with each linked-list representing macroblocks of a group having the same reference parameters. The hardware accelerator may be programmed to accelerate motion compensation by reconstructing macroblocks of the destination frame group-wise in the indexed order of the array of linked-lists.

Abstract: A method, user equipment, network equipment and a system for initiating a wireless connection and subsequent communication over a shared physical resource in a wireless communication system between user equipment and network equipment comprising: processing a UE-derived temporary identifier; communicating the temporary identifier as an identifier to the network equipment; communicating a downlink message conveying the temporary identifier and a description of a scheduled resource on a shared channel, the scheduled resource comprising a resource allocated to the user equipment by the network equipment; and communicating data on the scheduled resource in response to the downlink message.

Abstract: One embodiment of the present invention sets forth a mechanism for managing thread divergence in a thread group executing a multithreaded processor. A unanimous branch instruction, when executed, causes all the active threads in the thread group to branch only when each thread in the thread group agrees to take the branch. In such a manner, thread divergence is eliminated. A branch-any instruction, when executed, causes all the active threads in the thread group to branch when at least one thread in the thread group agrees to take the branch.

Abstract: A method of generating an image. The method includes simulating a presence of at least one light source within a virtualized three dimensional space. Within the virtualized three dimensional space, a light sensing plane is defined. The light sensing plane includes a matrix of a number of pixels to be displayed on a display screen. The method further includes using a light transport procedure, computing a gradient value for each pixel of the matrix to produce a number of gradient values. The gradient computation involves selecting a plurality of light path pairs that contribute to a pixel wherein the selection is biased towards selection of more light paths that pass through pixels having larger gradient values. The plurality of gradient values are converted to a plurality of light intensity values which represent the image.

Abstract: A system and method are provided for synchronizing threads in a divergent region of code within a multi-threaded parallel processing system. The method includes, prior to any thread entering a divergent region, generating a count that represents a number of threads that will enter the divergent region. The method also includes using the count within the divergent region to synchronize the threads in the divergent region.

Abstract: A graphics processing subsystem and a method of shading. In one embodiment, the subsystem includes: (1) a memory configured to contain a texel data structure according to which multiple primitive texels corresponding to a particular composite texel are contained in a single page of the memory and (2) a graphics processing unit configured to communicate with the memory via a data bus and execute a shader to fetch the multiple primitive texels contained in the single page to create the particular composite texel.

Abstract: A system and method for stereoscopic image capture. The method includes capturing a first image with a first camera and capturing a second image with a second camera. The second camera comprises a lower resolution sensor than a sensor of the first camera. The method further includes determining a third image based on adjusting the first image to a resolution of the lower resolution sensor of the second camera and generating a stereoscopic image comprising the second image and the third image.