Abstract: A system and method for compressing stencil data attendant to rendering an image. In one embodiment, the method includes: (1) selecting a base stencil value for a particular group, (2) selecting a single-bit delta value for each sample in the particular group and (3) storing the stencil base value and the delta values in a frame buffer.

Abstract: A system, method, and computer program product are provided for invalidating cache lines. In use, one or more cache lines that hold data from within a region of a memory address space are invalidated.

Abstract: A system, method, and computer program product are provided for calculating settings for a device, utilizing one or more constraints. In use, a plurality of parameters associated with a device is identified. Additionally, one or more constraints are determined, utilizing the plurality of parameters. Further, one or more settings are calculated for the device, utilizing the one or more constraints and the plurality of parameters.

Abstract: A system, method, and computer program product are provided for determining settings for a device. In use, a plurality of parameters associated with a device is identified. Additionally, one or more settings associated with the device are determined, based on the plurality of parameters.

Abstract: A system, method, and computer program product are provided for simultaneously determining settings for a plurality of parameter variations. In use, a plurality of parameter variations associated with a device is identified. Additionally, settings for each of the plurality of parameter variations are determined simultaneously.

Abstract: A system, method, and computer program product are provided for determining whether parameter configurations meet predetermined criteria. In use, predetermined criteria associated with a software element are identified. Additionally, it is determined whether each of a plurality of different parameter configurations meets the criteria, utilizing a directed acyclic graph (DAG).

Abstract: A system, method, and computer program product are provided for single wire voltage control of a voltage controller. A voltage controller is included and is in communication with a device, A single wire is connected between the voltage controller and the device for use by the device in controlling an output voltage of the voltage controller.

Abstract: A mobile radio communications network for communicating broadcast data to a plurality of mobile communications devices by transmitting and receiving the broadcast data via a wireless access interface includes one or more base stations for transmitting signals to and receiving signals from mobile communications devices attached to the base stations, and a relay node arranged in operation to receive a first signal representing the broadcast data transmitted by one of the base stations to the relay node via a first down-link channel of the wireless access network, and to retransmit the broadcast data as a second signal for reception by one or more of the mobile communications devices via a second channel of the wireless access network.

Abstract: A system, method, and computer program product are provided for testing device parameters. In use, a plurality of device parameters is determined, utilizing a directed acyclic graph (DAG). Further, the determined plurality of device parameters is tested.

Abstract: One embodiment of the present invention sets forth a technique for performing a memory access request to compressed data within a virtually mapped memory system comprising an arbitrary number of partitions. A virtual address is mapped to a linear physical address, specified by a page table entry (PTE). The PTE is configured to store compression attributes, which are used to locate compression status for a corresponding physical memory page within a compression status bit cache. The compression status bit cache operates in conjunction with a compression status bit backing store. If compression status is available from the compression status bit cache, then the memory access request proceeds using the compression status. If the compression status bit cache misses, then the miss triggers a fill operation from the backing store. After the fill completes, memory access proceeds using the newly filled compression status information.

Abstract: One embodiment of the invention sets forth a CROP configured to perform both color raster operations and atomic transactions. Upon receiving an atomic transaction, the distribution unit within the CROP transmits a read request to the L2 cache for retrieving the destination operand. The distribution unit also transmits the source operands and the operation code to the latency buffer for storage until the destination operand is retrieved from the L2 cache. The processing pipeline transmits the operation code, the source and destination operands and an atomic flag to the blend unit for processing. The blend unit performs the atomic transaction on the source and destination operands based on the operation code and returns the result of the atomic transaction to the processing pipeline for storage in the internal cache. The processing pipeline writes the result of the atomic transaction to the L2 cache for storage at the memory location associated with the atomic transaction.

Abstract: One embodiment of the present invention sets forth a technique for dynamically specifying a texture header and texture sampler using an index. The index corresponds to a particular register value that may be static or computed during execution of a shader program. Any texture operation instruction may specify an index value for each of the texture header and the texture sampler.

Abstract: A method and system for graphics instruction fetching. The method includes executing a plurality of threads in a multithreaded execution environment. A respective plurality of instructions are fetched to support the execution of the threads. During runtime, at least one instruction is prefetched for one of the threads to a prefetch buffer. The at least one instruction is accessed from the prefetch buffer if required by the one thread and discarded if not required by the one thread.

Abstract: A method includes implementing, with a memory of a computing device, a memory controller of the memory of the computing device, a storage device coupled to the computing device and/or an external device coupled to the computing device, a scheme for detecting an overlap between a first address range and a second address range. The first address range includes a first starting address and a first ending address, and the second address range includes a second starting address and a second ending address. The method also includes reducing a number of comparators utilized in the address range overlap detection through solely determining whether the first starting address is within the second address range or the second starting address is within the first address range.

Abstract: A system includes a processor having an instruction register for storing an instruction having a predefined opcode, a predicate register for storing a predicate condition to select an output register for a result of the instruction, a first output register, and a second output register. The processor further includes processor circuitry operable to execute the instruction to produce a result, and processor circuitry operable to store the result of the instruction in the first output register if the predicate condition to select the output is true, and to store the second output register if the predicate condition to select the output is false. A single instruction is used to produce the result, and to store the result of the instruction.

Abstract: An interposer having decaps formed in blind-vias, a packaged semiconductor structure having decaps formed in blind-vias, and methods for forming the same are provided. In one embodiment, an interposer is provided that includes an interconnect layer disposed on a substrate. A plurality of through-vias are formed through the substrate in an isolated region of the substrate. At least one of the plurality of conductive vias are electrically coupled to at least one of a plurality of top wires formed in the interconnect layer. A plurality of blind-vias are formed through the substrate in a dense region of the substrate during a common etching step with the through-vias. At least one blind-via includes (a) a dielectric material lining the blind-vias, and (b) a conductive material filling the lined blind-vias and forming a decoupling capacitor.

Abstract: The present invention provides a flexible encryption device, comprising N encryption units connected in series for encrypting N-bit input data, each one of the N encryption units further comprising an exclusive-OR gate for receiving an input data; and a flip-flop connected coupled to the exclusive-OR gate. Furthermore, the present invention also provides the data transferring system that can be easily modified without the needs of manual intervention.

Abstract: One embodiment of the present invention sets forth a technique for reducing the amount of memory required to store vertex data processed within a processing pipeline that includes a plurality of shading engines. The method includes determining a first active shading engine and a second active shading engine included within the processing pipeline, wherein the second active shading engine receives vertex data output by the first active shading engine. An output map is received and indicates one or more attributes that are included in the vertex data and output by the first active shading engine. An input map is received and indicates one or more attributes that are included in the vertex data and received by the second active shading engine from the first active shading engine.

Abstract: A method for supporting broadcast transmission in a wireless communication system (200) that comprises a plurality of communication cells, with broadcast content being routed from a base station (210) to at least one wireless communication unit (225, 226) via at least one relay node (RN) (224) is described. The method comprises, at the base station (210) broadcasting the broadcast content from the base station (210) to at least one from a group consisting of: the at least one RN (224), the at least one wireless communication unit (226); and supplementing the broadcast transmission with at least one augmented unicast transmission associated with the broadcast content. A base station (210), an integrated circuit and a non-transitory computer program product comprising executable program code are also described. A relay node (224), an integrated circuit, a method performed at the relay node and a non-transitory computer program product comprising executable program code are also described.

Abstract: A method includes providing, in a camera system, a flash light including one or more Light Emitting Diodes (LEDs) having color changing ability based on the one or more LEDs being constituted by a combination of semiconductor compounds, and providing a user interface on the camera system to enable a user of the camera system to modify a number of settings on the camera system. The method also includes modifying, through a flash light driver component, an intensity level of the flash light and/or a voltage supplied thereto through a flash light driver circuit of the flash light in accordance with an appropriate modified setting by the user on the user interface. The modification of the voltage supplied to the flash light enables an appropriate modification of a color of a light emitted by the flash light.