Abstract: A method is described for reception of broadcast transmission in a wireless communication system (200) that comprises a plurality of communication cells, with broadcast content being routed from a base station (210) to at least one wireless communication unit (225, 226) via at least one relay node (RN) (224). The method comprises, at the at least one wireless communication unit (226) receiving a broadcast transmission of broadcast content from at least one from a group consisting of: the base station (210) and the at least one relay node (RN) (224); and receiving a supplementary at least one augmented unicast transmission from at least one from a group consisting of: the base station (210) and the at least one relay node (RN) (224); wherein the at least one augmented unicast transmission is associated with the broadcast content. A wireless communication unit (226), an integrated circuit and a non-transitory computer program product comprising executable program code are also described.

Abstract: One embodiment of the present invention sets forth a mechanism for managing thread divergence in a thread group executing a multithreaded processor. A unanimous branch instruction, when executed, causes all the active threads in the thread group to branch only when each thread in the thread group agrees to take the branch. In such a manner, thread divergence is eliminated. A branch-any instruction, when executed, causes all the active threads in the thread group to branch when at least one thread in the thread group agrees to take the branch.

Abstract: Systems and methods for encoding/decoding a data word using an 8b/9b encoding scheme that eliminates two-aggressor crosstalk are disclosed. The 8b/9b encoding scheme enables a data word to be encoded using code words. Each of the valid code words does not include any three consecutive bits having a logic level of logic-high (i.e., ‘1’), and represent transition vectors for consecutive symbols transmitted over the high speed parallel bus. An encoder and corresponding decoder are disclosed for implementing the 8b/9b encoding scheme. In one embodiment, the encoder/decoder implements a modified Fibonacci sequence algorithm. In another embodiment, the encoder/decoder implements a look-up table.

Abstract: The invention set forth herein describes a mechanism for efficiently performing extended precision operations on multi-word source operands. Corresponding data words of the source operands are processed together via each instruction of a cascading sequence of instructions. State information generated when each instruction is processed is stored in condition code flags. The state information is optionally used in the processing of subsequent instructions in the sequence and/or accumulated with previously set state information.

Abstract: One embodiment of the present invention sets forth a technique for partitioning a predecessor thread program into sub-programs and dynamically spawning a thread grid of the sub-programs based on the outcome of a conditional statement in the predecessor thread program. The programming instructions for the predecessor thread program are analyzed to assess the benefit of partitioning the thread program at a conditional statement into sub-programs. If the predecessor thread program is partitioned, then each branch of the conditional statement may be used to form a separate sub-program. Predicate tables are populated at the predecessor thread program run-time to establish which possible instances of the thread sub-programs should be spawned in subsequent execution phases.

Abstract: A computer system and a method of operating a service-processor-centric computer system. In one embodiment, the computer system includes: (1) a CPU configured to issue control signals and (2) a service processor configured for intercepting and handling the control signals, the handling including delaying, modifying or ignoring the control signals, the service processor further configuring for issuing highest-priority control signals.

Abstract: A system, method, and computer program product are provided for determining a monotonic set of presets. In use, a plurality of parameters associated with a product or service is identified. Additionally, a monotonic set of presets associated with the product or service are determined, based on the plurality of parameters.

Abstract: A method includes querying a database to determine the color profile of the multimedia content. The method may include comparing the secondary color profile of the secondary display to the primary color profile of the primary display and then determining a secondary color profile to apply to the multimedia content on the secondary display. The method may include selecting the secondary color profile from a database and applying the secondary color profile to the multimedia content. The method includes displaying the multimedia content with the secondary color profile on secondary display to reduce a color discrepancy of the multimedia content between the primary and the secondary display.

Abstract: One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core GPU are converted by a translator for execution by a general purpose CPU. The application program is partitioned into regions of synchronization independent instructions. The instructions are classified as convergent or divergent and divergent memory references that are shared between regions are replicated. Thread loops are inserted to ensure correct sharing of memory between various threads during execution by the general purpose CPU.

Abstract: A system and method for facilitating access to graphics memory wherein the graphics memory can be shared between a graphics processor and general system application. The method includes detecting an idle state of a graphics processing unit (GPU). The GPU uses graphics memory operable for storing graphics data. The method further includes determining an amount of available memory of the graphics memory of the GPU and signaling an operating system regarding the available memory. Memory data transfers are then received to store data into the available memory of the graphics memory wherein the data is related to general system application. Memory accesses to the available memory of the GPU are translated into a suitable format and executed so that the graphics memory is shared between the GPU and the operating system.

Abstract: A method, apparatus, and system of using call termination to communicate a message are disclosed. In one embodiment, a system of a telecommunications network includes a mobile station associated with the telecommunications network, a switching module of the telecommunications network to establish a call between a communication device and the mobile station, a call termination module of the mobile station to determine if the mobile station is in a call termination mode and to communicate a communication protocol to the switching module to cause the switching module to terminate the call if the mobile station is in the call termination mode, and a message module of the telecommunications network to communicate a message to the communication device.

Abstract: One embodiment of the present invention sets forth a mechanism for transmitting and receiving ground-referenced single-ended signals. A transmitter combines a direct current (DC) to DC converter including a flying capacitor with a 2:1 clocked multiplexer to drive a single-ended signaling line. The transmitter drives a pair of voltages that are symmetric about the ground power supply level. Signaling currents are returned to the ground plane to minimize the generation of noise that is a source of crosstalk between different signaling lines. Noise introduced through the power supply is correlated with the switching rate of the data and may be reduced using an equalizer circuit.

Abstract: A mobile communications system comprises a first group of one or more base stations which are arranged to communicate signals with mobile units via a wireless access interface by transmitting and/or receiving radio signals within a first frequency band; a second group of one or more base stations which are arranged to communicate signals with mobile units via a wireless access interface by transmitting and/or receiving radio signals within a second frequency band; and a controller.

Abstract: In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured to maintain power when the device is placed in a low-power mode. A plurality of input output blocks are included in the device and are for receiving external inputs for the integrated circuit device and for providing outputs from the integrated circuit device. The power circuit is coupled to provide power to at least one of the input output blocks to maintain state when the integrated circuit device is in the low-power mode.

Abstract: One embodiment of the present invention sets forth a technique for reducing jitter caused by changes in a power supply for a clock generated by a ring oscillator of inverter devices. An inverter sub-circuit is coupled in parallel with a current-starved inverter sub-circuit to produce an inverter circuit that is insensitive to changes in the power supply voltage. When the ring oscillator is used as the voltage controlled oscillator of a phase locked loop, the delay of the inverters may be controlled by varying a bias current for each inverter in response to changes in the power supply voltage to reduce any jitter in a clock output produced by the changes in the power supply voltage. When the transistor devices are sized appropriately and the bias current is adjusted, the sensitivity of the inverter circuit to changes in the power supply voltage may be reduced.

Abstract: A method for executing video encoding operations. The method includes encoding an incoming video stream into a plurality of macro blocks by using a video encoder and receiving a box out slice map specification for the plurality of macro blocks. The box out slice map specification is converted to a foreground-background slice map specification. The plurality of macro blocks are then processed in accordance with the foreground-background specification and by using a common hardware encoder front end.

Abstract: A system and method for dynamically adjusting the pixel sampling rate during primitive shading can improve image quality or increase shading performance. Hybrid antialiasing is performed by selecting a number of shaded samples per pixel fragment. A combination of supersample and multisample antialiasing is used where a cluster of sub-pixel samples (multisamples) is processed for each pass through a fragment shader pipeline. The number of shader passes and multisamples in each cluster can be determined dynamically for each primitive based on rendering state.

Abstract: One embodiment of the present invention sets forth a technique for warping uniformly generated barycentric parameters to compensate for perspective foreshortening during tessellation of a geometric object. Near and far step sizes are computed for each edge of the geometric object. A warp equation is associated with each edge. Coefficients for each warp equation are computed from near and far step size for a corresponding edge. Uniformly generated barycentric parameters for each edge comprise an input variable for each corresponding warp equation. Warp equation outputs for edges of the geometric object are blended together using a linear blend function to generate vertices comprising geometric tessellation samples from the geometric object.

Abstract: One embodiment of the present invention sets forth a technique for technique for capturing and storing a level of an input signal using a dual-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations. The dual-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant. One of the clock signals may be a low-frequency “keeper clock” that toggles less frequently than the other two clock signal that is input to two transistor gates. The output signal Q is set or reset at the rising clock edge using separate trigger sub-circuits. Either the set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock.

Abstract: A method of debugging an application operable on a graphics pipeline subunit. A plurality of draw call groups is accessed. Each draw call group comprises a respective plurality of draw calls, sharing common state attributes of a prescribed state. The plurality of selectable draw call groups is displayed. In response to a user selection, a plurality of selectable draw calls associated with the selected draw call group is displayed. A plurality of selectable graphics pipeline subunits is displayed. In response to a user selection of a selected subunit, a plurality of editable state information and graphical primitives associated with a selected draw call are displayed. The plurality of editable state information may be grouped such that a portion sharing common attributes of the prescribed state are in one group. In response to a user selection, changes may be made to the selected draw call or the selected draw call group.