Abstract: The invention provides a method for driving a graphic processing unit (GPU). The method comprises the steps of: (a) receiving a plurality of requests for processing a first frame, a second frame and a third frame; (b) sequentially rendering the first frame and the third frame; (c) performing an interpolation to generate the second frame according to the rendered first frame and the rendered third frame; and, (d) sequentially displaying the rendered first frame, the second frame generated by interpolation and the rendered third frame.

Abstract: The invention provides a method for adaptively adjusting a framerate of a graphic processing unit (GPU). For example, when the GPU workload is high and the temperature of the GPU is close to high temperature, the framerate can be decreased to reduce the workload; when the GPU workload is low, the framerate can be permitted to increase to raise the workload. By the present invention, the GPU is permitted to operate at maximum temperature. The method comprises the steps of: (a) receiving an execution parameter associated with at least one GPU; (b) comparing if the execution parameter is greater than a first reference value; and (c) in the event the execution parameter is greater than the first reference value, increasing a sleep time and power-gating the at least one GPU based on the sleep time to adjust the framerate.

Abstract: A system and method are provided for launching a callable function. A processing system includes a host processor, a graphics processing unit, and a driver for launching a callable function. The driver is adapted to recognize at load time of a program that a first function within the program is a callable function. The driver is further adapted to generate a second function. The second function is adapted to receive arguments and translate the arguments from a calling convention for launching a function into a calling convention for calling a callable function. The second function is further adapted to call the first function using the translated arguments. The driver is also adapted to receive from the host processor or the GPU a procedure call representing a launch of the first function and, in response, launch the second function.

Abstract: A system and method for facilitating increased graphics processing without deadlock. Embodiments of the present invention provide storage for execution unit pipeline results (e.g., texture pipeline results). The storage allows increased processing of multiple threads as a texture unit may be used to store information while corresponding locations of the register file are available for reallocation to other threads. Embodiments further provide for preventing deadlock by limiting the number of requests and ensuring that a set of requests is not issued unless there are resources available to complete each request of the set of requests. Embodiments of the present invention thus provide for deadlock free increased performance.

Abstract: A system for ordering packets. The system includes a first memory, e.g., FIFO, storing transition information for posted packets, e.g., 1 when a posted packet transitions from a non-posted packet and 0 otherwise. A second memory stores transition information for non-posted packets, e.g., 1 when a non-posted packet transitions from a posted packet and 0 otherwise. A counter increments responsive to detecting a transition in the first memory and decrements responsive to detecting a transition in the second memory. A controller orders a posted packet for transmission prior to a non-posted packet if a value of the counter is negative and when a transitional value associated with the non-posted packet is 1, and wherein the controller orders either a posted packet or a non-posted packet otherwise. The first and the second memory may be within a same memory component.

Abstract: A method for comparator based quantization acceleration for an encoding process. The method includes computing coefficients for a discrete cosine transform encoding operation and determining a quantization step for use with a quantization operation for each of the coefficients. The method further includes determining each of the coefficients that are less than or equal to one half the quantization step by using a comparator configured in accordance with the quantization step. For the coefficients that are less than or equal to one half the quantization step, a quantized output value is transmitted to the encoding process. For the coefficients that are greater than one half the quantization step, the quantized output value is determined by executing multiplication logic to compute the quantized output value and transmit the computed quantized output value to the encoding process.

Abstract: Arbitrary size texture palettes. A texture palette storage embodied in a computer readable medium is provided. The texture palette storage is partitioned into texture palette tables of arbitrary size. Texel data is stored for each of the texture palette tables in the texture palette storage. Another aspect is a palette memory that receives a texture index value of y-bits. The palette memory comprises subtables of different length. Each sub-table has a range with a start address and a length. The start address is a multiple of m. Each range is of a length addressable by y-bits. The palette memory also includes a sub-table index value of x-bits.

Abstract: One embodiment sets forth a technique for on-chip satisfying timing requirements of on-chip source-synchronous, CMOS-repeater-based interconnect. Each channel of the on-chip interconnect may include one or more redundant wires. Calibration logic is configured to apply transition patterns to wires comprising each channel and calibration patterns that are generated in response to the transition patterns are captured. Based on the calibration patterns, wires that best satisfy the timing requirements of the on-chip interconnect are selected for use to transmit data. The calibration logic also trims the delays of the clock and selected data wires based on captured calibration patterns to improve the timing margin of the on-chip interconnect. Improving the timing margin of the on-chip interconnect improves chip yields.

Abstract: A method for identifying a failed network interface card in a system having two NICs configured as a team includes the steps of transmitting a first data packet from the first NIC to a third NIC, wherein the third NIC is not a member of the team, and transmitting a second data packet from the first NIC to the second NIC or from the second NIC to the third NIC, depending on whether the third NIC responds to the transmission of the first data packet. One advantage of the disclosed method is that it specifically identifies which NIC within the team has failed, which is something that cannot be determined by simply exchanging packets between the two NICs.

Abstract: A latency tolerant system for executing video processing operations. The system includes a host interface for implementing communication between the video processor and a host CPU, a scalar execution unit coupled to the host interface and configured to execute scalar video processing operations, and a vector execution unit coupled to the host interface and configured to execute vector video processing operations. A command FIFO is included for enabling the vector execution unit to operate on a demand driven basis by accessing the memory command FIFO. A memory interface is included for implementing communication between the video processor and a frame buffer memory. A DMA engine is built into the memory interface for implementing DMA transfers between a plurality of different memory locations and for loading the command FIFO with data and instructions for the vector execution unit.

Abstract: Provided herein is a voltage level shifter, an apparatus including a voltage level shifter and a method of converting voltages between input and output power domains. In one embodiment, the voltage level shifter includes: (1) an input circuit configured to receive a data signal from an input power domain and a power down signal from a output power domain and (2) a transition circuit coupled to the input circuit and configured to receive the data signal and an inverted signal of the power down signal, wherein the input circuit and the transition circuit are both configured to connect to a supply voltage of the output power domain as a power source.

Abstract: Method, receiver and computer program product for decoding a coded data block received at the receiver are disclosed. A first plurality of coded data bits representing the coded data block are received. First soft information values are determined corresponding to respective ones of the received first plurality of coded data bits, wherein each of the soft information values indicates a likelihood of a corresponding coded data bit having a particular value. An attempt is made to decode the coded data block using the first soft information values. The first soft information values are compressed. The compressed first soft information values are stored in a data store. A second plurality of coded data bits representing the coded data block is received and second soft information values corresponding to respective ones of the received second plurality of coded data bits are determined. The compressed first soft information values are retrieved from the data store and decompressed.

Abstract: A modem and a method of placing a modem in an online data state. In one embodiment, the modem includes: (1) a digital interface configured to receive, via an AT channel thereof, a standard AT command directing an AT channel of the modem to exit a command state and enter an online data state and (2) a command processor coupled to the digital interface and configured to: extract channel designation data received as a standard parameter of the standard AT command, cause a channel designated by the channel designation data and separate from the AT channel to enter the online data state, and allow the AT channel to remain in the command state.

Abstract: Systems and methods for performing optical image processing via a transparent display are disclosed. In one example approach, a method comprises determining a position of incident light on a see-through display device, determining a direction of the incident light relative to the see-through display device, and modulating, with the see-through display device, a transmission of the incident light through the see-through display device based on the determined position and determined direction of the incident light.

Abstract: A column select multiplexer, a method of reading data from a random-access memory and a memory subsystem incorporating the multiplexer or the method. In one embodiment, the column select multiplexer includes: (1) a first field-effect transistor having a gate coupled via an inverter to a bitline of a static random-access memory array, (2) a second field-effect transistor coupled in series with the first field-effect transistor and having a gate coupled to a column select bus of the static random-access memory array and (3) a latch having an input coupled to the first and second field-effect transistors.

Abstract: A floating-point unit and a method of identifying exception cases in a floating-point unit. In one embodiment, the floating-point unit includes: (1) a floating-point computation circuit having a normal path and an exception path and operable to execute an operation on an operand and (2) a decision circuit associated with the normal path and the exception path and configured to employ a flush-to-zero mode of the floating-point unit to determine which one of the normal path and the exception path is appropriate for carrying out the operation on the operand.

Abstract: A method for implementing multi context execution on a video processor having a scalar execution unit and a vector execution unit. The method includes allocating a first task to a vector execution unit and allocating a second task to the vector execution unit. The first task is from a first context in the second task is from a second context. The method further includes interleaving a plurality of work packages comprising the first task and the second task to generate a combined work package stream. The combined work package stream is subsequently executed on the vector execution unit.

Abstract: A memory controller for prefetching data for a processor, or CPU, of a computer system. The memory controller functions by interfacing the processor to system memory via a system memory bus. A prefetch cache is included in the memory controller. The prefetch cache includes a short-term storage portion and a long-term storage portion. The prefetch cache is configured to access system memory to retrieve and store a plurality of sequential cache lines subsequent to a processor access to system memory.

Abstract: A video navigation system and method can be utilized to efficiently and adjustably navigate video content. In one embodiment, a video information control method facilitates efficient video navigation. A video stream is received and video access point selection between multiple access points in said video stream is controlled. The presentation information is forwarded for each of the multiple access points. In one exemplary implementation, the presentation information is forwarded to a display and the information is directed to presenting a main viewing area and navigation areas that present looping video clips or portions of the video stream at time intervals ahead of and behind the video portion being presented in the main viewing area.

Abstract: An error locator unit for correcting two bit error. The error locator unit includes a plurality of operational units, a normalized basis transform unit, and a conversion unit. The plurality of operations units calculates coefficients of the polynomial based on the generated syndromes in a first basis of a Galois Field. Operating on the coefficients produces a root definition value vector in the first basis. The normalized basis transform unit transforms the root definition value vector to a normal basis to produce a plurality of roots. The conversion unit converts the plurality of roots to the first basis. A scaling factor calculated based on the coefficients is applied to the output of the conversion unit to produce a plurality of scaled roots for said polynomial in the first basis. The plurality of scaled roots is added to produce error locations for the polynomial.