Abstract: A system and method for compiling source code (e.g., with a compiler). The method includes accessing a portion of device source code and determining whether the portion of the device source code comprises a piece of work to be launched on a device from the device. The method further includes determining a plurality of application programming interface (API) calls based on the piece of work to be launched on the device and generating compiled code based on the plurality of API calls. The compiled code comprises a first portion operable to execute on a central processing unit (CPU) and a second portion operable to execute on the device (e.g., GPU).

Abstract: A system and method for detecting shared memory hazards are disclosed. The method includes, for a unit of hardware operating on a block of threads, mapping a plurality of shared memory locations assigned to the unit to a tracking table. The tracking table comprises an initialization bit as well as access type information, collectively called the state tracking bits for each shared memory location. The method also includes, for an instruction of a program within a barrier region, identifying a second access to a location in shared memory within a block of threads executed by the hardware unit. The second access is identified based on a status of the state tracking bits. The method also includes determining a hazard based on a first type of access and a second type of access to the shared memory location. Information related to the first access is provided in the table.

Abstract: A system and method for detecting, filtering, prioritizing and reporting shared memory hazards are disclosed. The method includes, for a unit of hardware operating on a block of threads, mapping a plurality of shared memory locations assigned to the unit to a tracking table. The tracking table comprises initialization information for each shared memory location. The method also includes, for an instruction of a program within a barrier region, identifying a potential conflict by identifying a second access to a location in shared memory within a block of threads executed by the hardware unit. First information associated with a first access and second information associated with the second access to the location is determined. Filter criteria is applied to the first and second information to determine whether the instruction causes a reportable hazard. The instruction is reported when it causes the reportable hazard.

Abstract: Embodiments of the present invention provide a novel solution to generate multiple linked device code portions within a final executable file. Embodiments of the present invention are operable to extract device code from their respective host object filesets and then link them together to form multiple linked device code portions. Also, using the identification process described by embodiments of the present invention, device code embedded within host objects may also be uniquely identified and linked in accordance with the protocols of conventional programming languages. Furthermore, these multiple linked device code portions may be then converted into distinct executable forms of code that may be encapsulated within a single executable file.

Abstract: A graphics card is provided. The graphics card comprises: a Graphics Processing Units (GPU) for data computing; and a wireless controller for wirelessly receiving data from other graphic cards or sending data to the other graphics cards, and communicating with the GPU by bus. The graphic card able provided by the present invention can provide a low-cost solution with more powerful computing capabilities to meet the demands for computing complex problems in the fields of commerce, industry, and science.

Abstract: Embodiments of the present invention provide a novel solution that supports the separate compilation of host code and device code used within a heterogeneous programming environment. Embodiments of the present invention are operable to link device code embedded within multiple host object files using a separate device linking operation. Embodiments of the present invention may extract device code from their respective host object files and then linked them together to form linked device code. This linked device code may then be embedded back into a host object generated by embodiments of the present invention which may then be passed to a host linker to form a host executable file. As such, device code may be split into multiple files and then linked together to form a final executable file by embodiments of the present invention.

Abstract: A switching power capable of avoiding coupling effects is provided. The switching power comprises a driving loop. The driving loop comprises the substrate end and the gate end of a power Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and a controlling gate, and the controlling gate is connected to the gate end of the power MOSFET and the substrate end of the power MOSFET is connected to the controlling gate. The switching power provided by the present can avoid the coupling effect of the driving loop and the power stage loop at the common source pin, thereby reducing the switching power losses and improving the efficiency of the switching power.

Abstract: A system, method, and computer program product are provided for controlling stereo glasses shutters. In use, a right eye shutter of stereo glasses is controlled to switch between a closed orientation and an open orientation. Further, a left eye shutter of the stereo glasses is controlled to switch between the closed orientation and the open orientation. To this end, the right eye shutter and the left eye shutter of the stereo glasses may be controlled such that the right eye shutter and the left eye shutter simultaneously remain in the closed orientation for a predetermined amount of time.

Abstract: A single display system and method are provided for displaying stereoscopic content. In particular, a single display mechanism capable of displaying stereoscopic content for viewing with passive glasses is provided.

Abstract: A server for use in connection with a network including at least one client and a communication link interconnecting the client and server. The server comprises a user interaction control module, an image rendering module and an interface. The image rendering module is configured to render, from three-dimensional scene data representing a scene, a two-dimensional image. The interface configured to transmit the two-dimensional image over the communication link to the client. The user interaction control module is configured to regulate interactions between the server, in particular the image rendering module, and respective clients who may be using the server concurrently to control images in which customizations requested by, for example, respective clients are rendered.

Abstract: Method, receiver and computer program product for processing a signal transmitted from a plurality of spatially separated transmit antennas using a Multiple-Input Multiple-Output transmission over a wireless network. The signal is received at a plurality of spatially separated receive antennas, the signal comprising a plurality of data streams and the quality/reliability of each of the data streams in the received signal is determined. Based on the determined quality/reliability of the data streams, a decoding technique is selected to be one of (i) a successive decoding technique for successively decoding data streams in which one of the data streams is decoded and a signal corresponding to said one of the data streams is removed from the received signal prior to decoding further data streams in the received signal, and (ii) a non-successive decoding technique in which each data stream is decoded from the received signal by treating the other data streams as noise in the received signal.

Abstract: In one embodiment, a microprocessor is provided. The microprocessor includes a cache that is controlled by a cache controller. The cache controller is configured to replace cachelines in the cache based on a replacement scheme that prioritizes the replacement of cachelines that are less likely to cause roll back of a transaction of the microprocessor.

Abstract: A system, method, and computer program product are provided for performing graph coloring. In use, a graph with a plurality of vertices is identified. Additionally, the plurality of vertices of the graph is categorized, where the categorizing of the plurality of vertices is optimized.

Abstract: A system, method, and computer program product are provided for performing graph coloring. In use, a graph with a plurality of vertices is identified. Additionally, the plurality of vertices of the graph is categorized, where the categorizing of the plurality of vertices is optimized.

Abstract: The server based graphics processing techniques, describer herein, include passing graphics commands from a shim layer to a guest display device interface, wherein the shim layer and the guest display device interface (DDI) are executing in a given instance of a guest virtual machine (VM). The guest DDI calls back to the shim layer with corresponding function calls. The function calls are passed from the shim layer to a host DDI through a communication channel of a host-guest communication manager (HGCM), wherein the host display device interface and host-guest communication manager are executing in a host virtual machine manager (VMM).

Abstract: A system, method, and computer program product are provided for performing graph aggregation. In use, a graph with a plurality of vertices and a plurality of edges is identified. Additionally, aggregation is performed on the vertices and edges of the graph by computing a graph matching, where such graph matching is performed in a data-parallel manner.

Abstract: Embodiments related to re-dispatching an instruction selected for re-execution from a buffer upon a microprocessor re-entering a particular execution location after runahead are provided. In one example, a microprocessor is provided. The example microprocessor includes fetch logic, one or more execution mechanisms for executing a retrieved instruction provided by the fetch logic, and scheduler logic for scheduling the retrieved instruction for execution. The example scheduler logic includes a buffer for storing the retrieved instruction and one or more additional instructions, the scheduler logic being configured, upon the microprocessor re-entering at a particular execution location after runahead, to re-dispatch, from the buffer, an instruction that has been previously dispatched to one of the execution mechanisms.

Abstract: A system, method, and computer program product are provided for performing graph aggregation. In use, a graph with a plurality of vertices and a plurality of edges is identified. Additionally, graph matching is performed on the vertices and edges of the graph by computing a graph matching, wherein the performance of the graph matching is optimized.

Abstract: A system, method, and computer program product are provided for controlling stereo glasses shutters. In use, a right eye shutter of stereo glasses is controlled to switch between a closed orientation and an open orientation. Further, a left eye shutter of the stereo glasses is controlled to switch between the closed orientation and the open orientation. To this end, the right eye shutter and the left eye shutter of the stereo glasses may be controlled such that the right eye shutter and the left eye shutter simultaneously remain in the closed orientation for a predetermined amount of time.

Abstract: An embodiment of a computing system is configured to process data using a multithreaded SIMD architecture that includes heterogeneous processing engines to execute a program. The program is constructed of various program instructions. A first type of the program instructions can only be executed by a first type of processing engine and a third type of program instructions can only be executed by a second type of processing engine. A second type of program instructions can be executed by the first and the second type of processing engines. An assignment unit may be configured to dynamically determine which of the two processing engines executes any program instructions of the second type in order to balance the workload between the heterogeneous processing engines.