Abstract: A method and system are implemented for verifying connection status information associated with a specific display attachment location. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of receiving a first signature representative of a first set of connection states tracked by a graphics subsystem associated with the display attachment location, authenticating whether the integrity of a content path including the display attachment location is maintained based on the first signature, and deciding whether to continue sending the content to the display attachment location so that requirements associated with protecting the content are satisfied.

Abstract: One embodiment of the present invention sets forth a technique for compressing color data. Color data for a tile including multiple samples is compressed based on an equality comparison and a threshold comparison based on a programmable threshold value. The equality comparison is performed on a first portion of the color data that includes at least exponent and sign fields of floating point format values or high order bits of integer format values. The threshold comparison is performed on a second portion of the color data that includes mantissa fields of floating point format values or low order bits of integer format values. The equality comparison and threshold comparison are used to select either computed averages of the pixel components or the original color data as the output color data for the tile. When the threshold is set to zero, only tiles that can be compressed without loss are compressed.

Abstract: A system and method for dynamically adjusting the pixel sampling rate during primitive shading can improve image quality or increase shading performance. Hybrid antialiasing is performed by selecting a number of shaded samples per pixel fragment. A combination of supersample and multisample antialiasing is used where a cluster of sub-pixel samples (multisamples) is processed for each pass through a fragment shader pipeline. The number of shader passes and multisamples in each cluster can be determined dynamically for each primitive based on rendering state.

Abstract: A raster unit generates graphic data for specific regions of a display device by processing each graphics primitive in a sequence of graphics primitives. A tile coalescer within the raster unit receives graphic data based on the sequence of graphics primitives processed by the raster unit. The tile coalescer collects graphic data for each region of the display device into a different bin before shading and then outputs each bin separately.

Abstract: A shared resource management system and method are described. In one embodiment a shared resource management system includes a plurality of engines, a shared resource, and a shared resource management unit. In one exemplary implementation the shared resource is a memory and the shared resource management unit is a memory management unit (MMU). The plurality of engines perform processing. The shared resource supports the processing. For example a memory store information and instructions for the engines. The shared resource management unit independently caches and invalidates page table entries on a per engine basis.

Abstract: A method including performing ray traversal wherein the ray traversal includes determining boxes intersected by a ray. The ray traversal includes performing a ray-box intersection test including calculating plane intersections, and determining comparisons of two operands wherein each operand is a binary representation of a floating point value and wherein further the determining comparisons operation is performed using an integer unit of the computer graphics system. The ray-box intersection test further includes, responsive to results of the comparisons, calculating span intersections of the boxes.

Abstract: The disclosure provides systems and methods for maintaining cache coherency in a multi-threaded processing environment. For each location in a data cache, a global state is maintained specifying the coherency of the cache location relative to other data caches and/or to a shared memory resource backing the data cache. For each cache location, thread state information associated with a plurality of threads is maintained. The thread state information is specified separately and in addition to the global state, and is used to individually control read and write permissions for each thread for the cache location. The thread state information is also used, for example by a cache controller, to control whether uncommitted transactions of threads relating to the cache location are to be rolled back.

Abstract: Embodiments of the present invention may be directed to an apparatus comprising a user interface device. The user interface device may include one or more peripheral units and a first circuit operable to create a pairing between the user interface device and a wireless computing device via a near-field wireless connection. The peripheral units may include a second circuit operable to create a wireless communication channel between the one or more peripheral units and the wireless computing device via a wireless communication protocol. The apparatus may also include an inductive charging pad operable for charging the wireless computing device. The inductive charging pad may generate a configuration eligibility signal indicating eligibility of the wireless computing device to connect to the one or more peripheral units upon the wireless computing device placed in proximity to the inductive charging pad.

Abstract: The invention discloses a semiconductor memory device and a method for word line decoding and routing. The present invention relates generally to semiconductor memory field, Problems solved by the invention is that, to improve the quality of word line signals results in routing congestion. Embodiments of the invention provide the program as follows: a semiconductor memory device and a method for word line decoding and routing, dividing memory array of the semiconductor memory device into a plurality of smaller memory arrays, on a first metal layer routing first decoded row address, on a second metal layer below the first metal layer routing second decoded row address, and the output word line after decoding drives the plurality of smaller memory allays, Embodiments of the invention are suitable for various semiconductor memory designs, including: on-chip cache, translation look-aside buffer, content addressable memory, ROM, EEPROM, and SRAM and so on.

Abstract: Embodiments of the present invention may be directed to an apparatus comprising a user interface docking device. The user interface docking device may include a first dock connector, a second dock connector, a battery, and a built-in keyboard. The first dock connector is operable to create a pairing between the user interface docking device and a wireless computing device. The second dock connector is operable to create a pairing between the user interface docking device and a mobile computer. The wireless computing device and mobile computer, when paired, are operable to combine resources for execution of tasks. The user interface docking device is operable to interact with content on the wireless computing device and the mobile computer. The apparatus may also include an inductive charging pad operable to facilitate a pairing between the number of peripheral units and user interface docking device via a near-field wireless connection.

Abstract: A shared memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for concurrently managing memory access requests from a plurality of engines. The shared memory management system independently controls access to the context memory without interference from other engine activities. In one exemplary implementation, the memory management unit tracks an identifier for each of the plurality of engines making a memory access request. The memory management unit associates each of the plurality of engines with particular translation information respectively. This translation information is specified by a block bind operation. In one embodiment the translation information is stored in a portion of instance memory. A memory management unit can be non-blocking and can also permit a hit under miss.

Abstract: An arithmetic logic stage in a graphics processor unit includes arithmetic logic units (ALUs) and global registers. The registers contain global values for a group of pixels. Global values may be read from any of the registers, regardless of which of the pixels is being operated on by the ALUs. However, when writing results of the ALU operations, only some of the global registers are candidates to be written to, depending on the pixel number. Accordingly, overwriting of data is prevented.

Abstract: Configurable bitstream engines are described that can operate to decode variable length decoding of video and audio bitstreams encoded using any of a plurality of encoding schemes. Systems and methods are described that allow functional components of a bitstream engine to be disabled, enabled and configured as necessitated by the encoding scheme used to encode a bitstream. Functional components of a bitstream engine can perform single actions and operations, repetitive actions and operations and sequences of actions and operations as desired. A bit field extraction process is described for extracting bit fields of specified length from memory, updating bit offsets, loading new data from memory when needed.

Abstract: A system and method for performing tessellation of three-dimensional surface patches performs some tessellation operations using programmable processing units and other tessellation operations using fixed function units with limited precision. (u,v) parameter coordinates for each vertex are computed using fixed function units to offload programmable processing engines. The (u,v) computation is a symmetric operation and is based on integer coordinates of the vertex, tessellation level of detail values, and a spacing mode.

Abstract: A memory access technique, in accordance with one embodiment of the present invention, includes coalescing mappings between virtual memory and physical memory when a contiguous plurality of virtual pages map to a contiguous plurality of physical pages. Any of the coalesced page table entries are sufficient to map all pages within the coalesced region. Accordingly, a memory subsystem can redirect one or more pending page table entry fetch requests to an appropriate coalesced page table entry.

Abstract: A method, a transmitter and a computer program product for processing data units at the transmitter are disclosed. In one embodiment, data units are transmitted to a receiver according to a protocol and with respective sequence numbers. The protocol indicates that the receiver is to use a reordering window to determine whether a data unit which is newly received from the transmitter is a new or repeated data unit the data stream by comparing the sequence numbers of the newly received data unit and a previously received data unit. A status report is received and based thereon, the sequence number of a next data unit to be transmitted in a new cell following a handover is selectively adjusted such that the next data unit will be determined to be a new data unit. The next data unit is transmitted with the adjusted sequence number to the receiver.

Abstract: An embodiment of a method for processing data units is provided that includes receiving a plurality of data units, of a data stream, having respective sequence numbers and, employing a reordering window, determining whether a newly received data unit of the data stream is a new data unit or a repeated data unit at the receiver and defining a first and a second range of sequence numbers relative to the sequence number of a previously received data unit. A newly received data unit is determined to be either a new or a repeated data unit based on whether the sequence number of the newly received data unit falls within the first or second range, and processed at the receiver based on this determination. A handover condition is detected, and in response thereto the first and second ranges of the reordering window are adjusted for use during the handover condition.

Abstract: An infrastructure apparatus for reducing interference, the apparatus comprising a controller. The controller is arranged in operation to determine an amount of interference in a first frequency band to radio signals for a first type of traffic caused by radio signals for a second type of traffic in a second frequency band, wherein the radio signals for the first type of traffic are to and/or from a first group of one or more base stations; and the radio signals for the second type of traffic are to and/or from a second group of one or more base stations. The controller is further arranged in operation to, in response to the determined interference, generate instructions to influence the second group in respect of the transmission of the radio signals for the second type of traffic in the second frequency, wherein the controller is further operable to generate the instructions using a priority for the first type of traffic and a priority for the second type of traffic.

Abstract: Image-based data, such as a block of texel data, is accessed. The data includes sets of color component values. A luminance value is computed for each set of color components values, generating a range of luminance values. A first set and a second set of color component values that correspond to the minimum and maximum luminance values are selected from the sets of color component values. A third set of color component values can be mapped to an index that identifies how the color component values of the third set can be decoded using the color component values of the first and second sets. The index value is selected by determining where the luminance value for the third set lies in the range of luminance values.

Abstract: The present invention provides a method of implementing an intra prediction computation applied to the H.264 digital video coding and a device. The method according to present invention of implementing the intra prediction computation applied to the H.264 video coding comprises selecting an image block to be intra-predicted and extracting the neighboring pixel values of said block; determining the prediction mode of said block, and perform first adding operation on said neighboring pixel values when the prediction mode is one of Diagonal_Down_Left, Diagonal_Down_Right, Vertical_Right, Horizontal_Down, Vertical_Left, and Horizontal_Up; performing first shifting operation and second adding operation on the result of first adding operation respectively; performing second shifting operation on the result of second adding operation; selecting a corresponding value to output from the results of first and second shifting operation according to said prediction mode and size of block.