Abstract: Systems and methods for estimating light transport between respective points includes selecting a plurality of first sub-paths extending the first point A. and selecting a plurality of second sub-paths extending from a second point B. A plurality of transport paths are constructed, wherein each one of the plurality of the first sub-paths is coupled to a respective one of the plurality of second paths, and wherein each transport path comprises one first sub-path and one second sub-path. Two or more of the transport paths are sampled, and a light transport value for each of the sampled transport paths is calculated to estimate the light transported between first point A and second point B.
Abstract: In one embodiment, a microprocessor is provided. The microprocessor includes instruction memory and a branch prediction unit. The branch prediction unit is configured to use information from the instruction memory to selectively power up the branch prediction unit from a powered-down state when fetched instruction data includes a branch instruction and maintain the branch prediction unit in the powered-down state when the fetched instruction data does not include a branch instruction in order to reduce power consumption of the microprocessor during instruction fetch operations.
Type:
Application
Filed:
April 27, 2012
Publication date:
October 31, 2013
Applicant:
NVIDIA CORPORATION
Inventors:
Aneesh Aggarwal, Ross Segelken, Kevin Koschoreck, Paul Wasson
Abstract: A method for setting costs for transmitting data associated with a machine-type communication (MTC) entity over a radio network in a wireless telecommunications system is described. The method comprises determining a transmission cost parameter representing a cost associated with transmitting data in the radio network and communicating the transmission cost parameter to the MTC entity. MTC entities using the radio network are thus able to manage their data transmissions based on transmission cost. Thus the radio network is able to dynamically manage traffic load by providing a cost incentive for transmitting MTC data when network resources are under utilised and applying a cost penalty for transmissions made while the network is relatively busy. Furthermore, the MTC entities of the wireless communication system are able to selected times and/or manner of data transmissions to reduce their overall cost of using the network.
Abstract: In one embodiment, a microprocessor is provided. The microprocessor includes a branch prediction unit. The branch prediction unit is configured to track the presence of branches in instruction data that is fetched from an instruction memory after a redirection at a target of a predicted taken branch. The branch prediction unit is selectively powered up from a powered-down state when the fetched instruction data includes a branch instruction and is maintained in the powered-down state when the fetched instruction data does not include an instruction branch in order to reduce power consumption of the microprocessor during instruction fetch operations.
Type:
Application
Filed:
April 27, 2012
Publication date:
October 31, 2013
Applicant:
NVIDIA CORPORATION
Inventors:
Aneesh Aggarwal, Ross Segelken, Paul Wasson
Abstract: A test system and method for low voltage differential signaling (LVDS) is provided. The system comprises: an input module for the user to input the information needed by the test; a communication module for connecting the control device 110 and the oscilloscope 120 using the communication means selected by the user; a measurement module for measure the parameters of the LVDS signal thought controlling a oscilloscope; an assessment module for assessing whether the obtained parameters of the LVDS signal comply with relevant LVDS specifications; and an output module for outputting the parameters of the LVDS signal and the assessment result of the parameters from the assessment module. The test system and method for LVDS provided by the present invention can advantageously meet the competitive needs in fast mass production and efficient engineering qualification.
Type:
Application
Filed:
July 12, 2012
Publication date:
October 31, 2013
Applicant:
NVIDIA CORPORATION
Inventors:
Xiaodong Han, Yi Zhou, Tao Hu, Ching Brendon Chau
Abstract: One embodiment of the present invention sets forth a method for enabling an intermediate code-based application program to access a target graphics processing unit (GPU) in a parallel processing environment. The method includes the steps of compiling a source code of the intermediate code-based application program to an intermediate code, translating the intermediate code to a PTX instruction code, and translating the PTX instruction code to a machine code executable by the target graphics processing unit before delivering the machine code to the target GPU.
Abstract: A system, method and associated data structure are provided for offloading upper protocol layer operations. In use, data is communicated over a network utilizing a plurality of protocols associated with a plurality of protocol layers, where the protocol layers include a network layer. Further, processing associated with the communicating is offloaded, at least in part. Such offloaded processing involves at least one protocol associated with at least one of the protocol layers situated at or above the network layer. Still yet, such offloading is performed statelessly.
Abstract: One embodiment of the present invention sets forth technique for watertight evaluation of Gregory patches for Catmull-Clark subdivision surfaces. Each boundary of each patch within a subdivision surface is configured to be owned by one related patch. In general, a given patch may own specific control points for the patch, while certain other control points for the patch may need to be reconstructed because the control points are owned by an adjacent patch. For a given patch, each control point along to a shared boundary is consistently generated using reconstruction data available to the patch. The reconstruction data is generated from values associated with a patch that owns the shared boundary. Because numerically identical data is used to evaluate each patch at each boundary, the boundaries are watertight. One advantage of the present invention is that watertight evaluation may be achieved using similar computational effort versus conventional non-watertight evaluation techniques.
Abstract: A software layer is disposed between an application and a driver. In use, the software layer is adapted to receive an object from the application intended to be rendered by a first graphics processor. Such software layer, in turn, routes the object to a second graphics processor, based on a policy.
Type:
Grant
Filed:
August 22, 2007
Date of Patent:
October 29, 2013
Assignee:
NVIDIA Corporation
Inventors:
David Wyatt, Lieven P. Leroy, Franck R. Diard
Abstract: One embodiment of the present invention sets forth a technique for translating application programs written using a parallel programming model for execution on multi-core graphics processing unit (GPU) for execution by general purpose central processing unit (CPU). Portions of the application program that rely on specific features of the multi-core GPU are converted by a translator for execution by a general purpose CPU. The application program is partitioned into regions of synchronization independent instructions. The instructions are classified as convergent or divergent and divergent memory references that are shared between regions are replicated. Thread loops are inserted to ensure correct sharing of memory between various threads during execution by the general purpose CPU.
Type:
Grant
Filed:
March 31, 2009
Date of Patent:
October 29, 2013
Assignee:
Nvidia Corporation
Inventors:
Vinod Grover, Bastiaan Joannes Matheus Aarts, Michael Murphy
Abstract: A method, computer-usable medium and a system for varying an incoming light field are disclosed. Embodiments provide mechanisms for performing image processing on an incoming light field using a spatial light modulator which is adjusted based upon characteristics of the incoming light field. The spatial light modulator may be positioned between the viewed scene and the eye, and therefore, may be semi-transparent. The image processing may consist of tone mapping, color enhancement, beautification, edge enhancement, spectral separation of colors, spectral separation of metamers, object emphasis, other image processing, or some combination thereof. Additionally, embodiments compensate for parallax errors by adjusting the spatial light modulator based upon the position of an observer with respect to the spatial light modulator.
Type:
Grant
Filed:
October 11, 2007
Date of Patent:
October 29, 2013
Assignee:
NVIDIA Corporation
Inventors:
David Patrick Luebke, Wolfgang Heidrich
Abstract: The invention sets forth an approach for aggregating a plurality of NICs in a computing device into a single logical NIC as seen by that computing device's operating system. The combination of the single logical NIC and a network resource manager provides a reliable and persistent interface to the operating system and to the network hardware, thereby improving the reliability and ease-of-configuration of the computing device. The invention also may improve communications security by supporting the 802.1X and the 802.1Q networking standards.
Type:
Grant
Filed:
December 15, 2005
Date of Patent:
October 29, 2013
Assignee:
Nvidia Corporation
Inventors:
Ashutosh K. Jha, Ayaz Abdulla, Hemamalini Manickavasagam, Anand Rajagopalan, Paul J. Sidenblad
Abstract: One embodiment of the present invention sets forth a destination credit management unit (CMU) that is coupled to source clients and a destination client and manages the transmission of credits associated with the destination client to the source clients. The destination CMU receives credits from the destination client as memory spaces within the destination client free up and transmits the credits to source clients as credits are consumed by the source clients. When a data packet is received from a source client, the destination CMU returns a credit to the source client if a credit is available. If a credit is not available, then the destination CMU stalls the source client until a credit becomes available. Credits are transmitted to stalled source clients in the order in which the source clients were stalled.
Abstract: A method and system for upgrading a software component in a computing device are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of storing a first software component in a first memory segment, maintaining a second software component in a second memory segment, wherein the second software component enables the computing device to boot up, and modifying at least one of a plurality of address lines to access the second memory segment after exiting a reset condition, if the execution of the first software component fails to satisfy a predetermined test condition.
Abstract: A system, method, and computer program product are provided for efficiently ray tracing micropolygon or other highly complex geometry. In operation, a first hierarchy of a plurality of objects is established. Additionally, rays are traced using the first hierarchy to efficiently identify which of the plurality of objects are potentially intersected. Furthermore, at least one of the potentially intersected objects are decomposed, on-demand, into a set of subobjects, each set of subobjects corresponding to one of the at least one of the potentially intersected objects. Still yet, a second hierarchy is established for at least one of the set of subobjects, the second hierarchy being determined by a connectivity of subobjects in an associated set of subobjects in order to accelerate ray tracing.
Type:
Grant
Filed:
May 12, 2009
Date of Patent:
October 29, 2013
Assignee:
NVIDIA Corporation
Inventors:
Johannes Hanika, Alexander Keller, Hendrik Lensch
Abstract: Systems and methods are disclosed for performing interactive debugging of shader programs using a non-preemptible graphics processing unit (GPU). An iterative process is employed to repeatedly re-launch a workload for processing by the shader program on the GPU. When the GPU encounters a hardware stop event, such as by reaching a breakpoint in any thread of the shader program, encountering a hardware exception, or failing a software assertion in the shader program, the state of any executing threads is saved, graphics memory is copied to system memory, and any currently executing threads are killed to enable the GPU to process graphics data for updating a display device. Each pass of the workload may result in incrementally more data being processed. In effect, the changing state and variable data resulting from each pass of the workload has the effect that the debugger is incrementally stepping through the shader program.
Type:
Grant
Filed:
March 9, 2012
Date of Patent:
October 29, 2013
Assignee:
Nvidia Corporation
Inventors:
Avinash Bantval Baliga, Gregory Paul Smith
Abstract: One embodiment of the present invention sets forth a method for executing a non-local return instruction in a parallel thread processor. The method comprises the steps of receiving, within the thread group, a first long jump instruction and, in response, popping a first token from the execution stack. The method also comprises determining whether the first token is a first long jump token that was pushed onto the execution stack when a first push instruction associated with the first long jump instruction was executed, and when the first token is the first long jump token, jumping to the second instruction based on the address specified by the first long jump token, or, when the first token is not the first long jump token, disabling the active thread until the first long jump token is popped from the execution stack.
Abstract: In a method of image signal processing, defective pixels are determined on-the-fly in a digital image representation based on a comparison of a pixel under evaluation with its surrounding pixels, with reference to a known resolving capability of a lens-sensor arrangement that captured the digital image representation. In response to the determination of defective pixels, the defective pixels are corrected.
Abstract: An aspect of the present invention reduces computational complexity in determining a illuminant of a scene of interest by selecting only a subset of illuminants from several more potential illuminants, and searching for a current illuminant for a present image frame in only the subset of illuminants. Computational complexity may be reduced due to the searching in fewer illuminants. The subset of illuminants are selected according to various aspects to enhance the probability that the closest matching potential illuminant is accurately determined. The features can be used in image capture devices (ICDs) such as video cameras.
Abstract: In a graphics pipeline of a graphics processor, a method for a unified primitive description for rasterization. The method includes receiving a group of primitives from a graphics application, wherein the group includes different types of primitives and the types of primitives include line primitives, point primitives and triangle primitives. For each of the types of primitives, the method includes generating a corresponding parallelogram, wherein the parallelogram has four sides disposed along an x-axis and a y-axis, and computing an inside y-axis mid point and an outside y-axis mid point based on the four sides. The parallelogram is controlled to represent to each of the primitive types respectively by adjusting a location of the inside y-axis mid point or the outside y-axis mid point.
Type:
Grant
Filed:
December 10, 2007
Date of Patent:
October 22, 2013
Assignee:
Nvidia Corporation
Inventors:
Edward A. Hutchins, William T. Warner, Jr., Christopher D. S. Donham