Patents Assigned to NVidia
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Publication number: 20250061978Abstract: In various examples, systems and methods are disclosed relating to using machine learning models to generate small molecules with desired structural or physicochemical properties with high sampling efficiency. In some implementations, one or more processors receive a data structure representing a first small molecule and encode the data structure into a latent distribution of a fixed size using a machine learning model, thereby determining an encoded representation of the data structure. To generate new molecules with similar properties to the first small molecule, the processors apply noise to the encoded representation to determine a modified encoded representation. The modified encoded representation is decoded to determine a modified data structure representing a second small molecule different from the first small molecule.Type: ApplicationFiled: August 16, 2023Publication date: February 20, 2025Applicant: NVIDIA CorporationInventors: Micha LIVNE, Danny Alexander REIDENBACH, Michelle Lynn GILL, Rajesh Kumar ILANGO, Yonatan ISRAELI
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Publication number: 20250061612Abstract: In various examples, systems and methods are disclosed relating to neural networks for synthetic data generation with discrete and continuous variable features. In training, an encoder can determine a plurality of encodings from a plurality of samples of training data, and the continuous generative model can operate as a decoder that is conditioned on the plurality of encodings to generate an estimated output to update the encoder and the continuous generative model. The discrete generative model can be trained over the plurality of encodings to learn to generate discrete variables corresponding to the distribution of information represented by the training data. At runtime, the discrete generative model can be used to generate a discrete variable from an input prompt, and can provide the discrete variable to the continuous generative model for the continuous generative model to generate an output, such an image, conditioned on the discrete variable.Type: ApplicationFiled: February 23, 2024Publication date: February 20, 2025Applicant: NVIDIA CorporationInventors: Karsten Julian KREIS, Arash VAHDAT, Yilun XU
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Patent number: 12229970Abstract: In examples, when attempting to interpolate or extrapolate a frame based on motion vectors of two adjacent frames, there can be more than one pixel value mapped to a given location in the frame. To select between conflicting pixel values for the given location, similarities between the motion vectors of source pixels that cause the conflict and global flow may be evaluated. For example, a level of similarity for a motion vector may be computed using a similarity metric based at least on a difference between an angle of a global motion vector and an angle of the motion vector. The similarity metric may also be based at least on a difference between a magnitude of the global motion vector and a magnitude of the motion vector. The similarity metric may weigh the difference between the angles in proportion to the magnitude of the global motion vector.Type: GrantFiled: August 15, 2022Date of Patent: February 18, 2025Assignee: NVIDIA CorporationInventors: Aurobinda Maharana, Karthick Sekkappan, Rohit Naskulwar
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Patent number: 12229566Abstract: Apparatuses, systems, and techniques to execute one or more application programming interfaces (APIs) to perform one or more operations for one or more accelerators within a heterogeneous processor. In at least one embodiment, one or more processors are to perform one or more instructions in response to one or more APIs to indicate one or more functions to be performed in response to one or more errors from one or more accelerators within a heterogeneous processor.Type: GrantFiled: November 28, 2022Date of Patent: February 18, 2025Assignee: NVIDIA CorporationInventors: Karthik Raghavan Ravi, Ashutosh Jain, Rahul Suresh
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Patent number: 12230245Abstract: Systems and methods provide for text normalization or inverse text normalization using a hybrid language system that combines rule-based processing with neural or learned processing. For example, a hybrid rule-based and neural approach identifies semiotic tokens within a textual input and generates a set of potential plain-text conversions of the semiotic tokens. The plain-text conversions are weighted and evaluated by a trained language model that rescores the plain-text conversion based on context to identify a highest scoring plain-text conversion for further processing within a language system pipeline.Type: GrantFiled: August 31, 2022Date of Patent: February 18, 2025Assignee: Nvidia CorporationInventors: Evelina Bakhturina, Yang Zhang, Boris Ginsburg
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Patent number: 12230040Abstract: State information can be determined for a subject that is robust to different inputs or conditions. For drowsiness, facial landmarks can be determined from captured image data and used to determine a set of blink parameters. These parameters can be used, such as with a temporal network, to estimate a state (e.g., drowsiness) of the subject. To improve robustness, an eye state determination network can determine eye state from the image data, without reliance on intermediate landmarks, that can be used, such as with another temporal network, to estimate the state of the subject. A weighted combination of these values can be used to determine an overall state of the subject. To improve accuracy, individual behavior patterns and context information can be utilized to account for variations in the data due to subject variation or current context rather than changes in state.Type: GrantFiled: November 21, 2023Date of Patent: February 18, 2025Assignee: Nvidia CorporationInventors: Yuzhuo Ren, Niranjan Avadhanam
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Patent number: 12231133Abstract: A time-to-digital converter (TDC) circuit includes self-referenced delay cell circuits each including: a first inverter coupled with a second inverter, the first inverter receiving a positive time signal representative of an incoming up signal; a third inverter coupled with a fourth inverter, the third inverter receiving a negative time signal representative of an incoming down signal; a first bank of capacitors coupled to a first node between the first/second inverters; and a second bank of capacitors coupled to a second node between the third/fourth inverters. Control logic generates first control signals, each with an up value, to selectively control the first bank of capacitors. Control logic generates second control signals, each with a down value, to selectively control the second bank of capacitors. The up values vary relative to the down values across the first control signals and the second control signals.Type: GrantFiled: May 9, 2023Date of Patent: February 18, 2025Assignee: NVIDIA CorporationInventor: Anish Morakhia
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Patent number: 12229869Abstract: One embodiment of a method rendering one or more graphics images includes tracing a ray cone through a three-dimensional (3D) graphics scene, generating a refracted ray cone based on the ray cone and a two-dimensional (2D) coordinate frame, and rendering a graphics image based on the refracted ray cone.Type: GrantFiled: May 25, 2021Date of Patent: February 18, 2025Assignee: NVIDIA CORPORATIONInventors: Tomas Akenine-Moller, Jakub Boksansky
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Publication number: 20250054288Abstract: Various examples relate to translating image labels from one domain (e.g., a synthetic domain) to another domain (e.g., a real-world domain) to improve model performance on real-world datasets and applications. Systems and methods are disclosed that provide an unsupervised label translator that may employ a generative adversarial network (GAN)-based approach. In contrast to conventional systems, the disclosed approach can employ a data-centric perspective that addresses systematic mismatches between datasets from different sources.Type: ApplicationFiled: August 7, 2023Publication date: February 13, 2025Applicant: NVIDIA CorporationInventors: Yuan-Hong LIAO, David Jesus ACUNA MARRERO, James LUCAS, Rafid MAHMOOD, Sanja FIDLER, Viraj Uday PRABHU
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Patent number: 12225665Abstract: A circuit system and method of manufacturing a printed circuit board includes providing an integrated circuit package mounted on a first side of a printed circuit board and a power regulator connected to power terminals of the integrated circuit package through a cutout in the printed circuit board. The power regulator draws power from the printed circuit board by way of side pins around a periphery of the cutout.Type: GrantFiled: May 5, 2022Date of Patent: February 11, 2025Assignee: NVIDIA Corp.Inventors: MingYi Yu, Greg Bodi, Ananta Attaluri
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Patent number: 12223303Abstract: Apparatuses, systems, and methods for verifying fingerprints associated with components to be installed on printed circuit boards (PCBs). In at least one embodiment, one or more processors determine whether a component fingerprint associated with a component to be installed on the PCB corresponds to an expected fingerprint, the component fingerprint based, at least in part, on a firmware version associated with the component.Type: GrantFiled: January 21, 2022Date of Patent: February 11, 2025Assignee: NVIDIA CorporationInventors: Benjamin Goska, Ryan Albright, William Andrew Mecham, William Ryan Weese, Aaron Richard Carkin, Michael Thompson
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Patent number: 12223949Abstract: A robotic system is provided for performing rearrangement tasks guided by a natural language instruction. The system can include a number of neural networks used to determine a selected rearrangement of the objects in accordance with the natural language instruction. A target object predictor network processes a point cloud of the scene and the natural language instruction to identify a set of query objects that are to-be-rearranged. A language conditioned prior network processes the point cloud, natural language instruction, and the set of query objects to sample a distribution of rearrangements to generate a number of sets of pose offsets for the set of query objects. A discriminator network then processes the samples to generate scores for the samples. The samples may be refined until a score for at least one of the sample generated by the discriminator network is above a threshold value.Type: GrantFiled: September 7, 2022Date of Patent: February 11, 2025Assignee: NVIDIA CorporationInventors: Christopher Jason Paxton, Weiyu Liu, Tucker Ryer Hermans, Dieter Fox
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Patent number: 12222820Abstract: A storage platform (100) improves data flow when modifying mirrored volumes. A backup storage component (120 A) that receives a service request keeps a copy of change data when redirecting the service request to a primary storage component (120B) that owns the volume that the service request targets. The primary storage (120B) component does not need to return the change data to the backup storage component (120A) when the primary storage component (120B) instructs the backup storage component (120 A) to apply the modification request to the backup copy of the volume.Type: GrantFiled: February 24, 2022Date of Patent: February 11, 2025Assignee: Nvidia CorporationInventors: Siamak Nazari, Jonathan Andrew McDowell, Philip Herron
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Patent number: 12223201Abstract: A hierarchical network enables access for a stacked memory system including or more memory dies that each include multiple memory tiles. The processor die includes multiple processing tiles that are stacked with the one or more memory die. The memory tiles that are vertically aligned with a processing tile are directly coupled to the processing tile and comprise the local memory block for the processing tile. The hierarchical network provides access paths for each processing tile to access the processing tile's local memory block, the local memory block coupled to a different processing tile within the same processing die, memory tiles in a different die stack, and memory tiles in a different device. The ratio of memory bandwidth (byte) to floating-point operation (B:F) may improve 50× for accessing the local memory block compared with conventional memory. Additionally, the energy consumed to transfer each bit may be reduced by 10×.Type: GrantFiled: February 9, 2024Date of Patent: February 11, 2025Assignee: NVIDIA CorporationInventors: William James Dally, Carl Thomas Gray, Stephen W. Keckler, James Michael O'Connor
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Patent number: 12223593Abstract: A high-definition map system receives sensor data from vehicles travelling along routes and combines the data to generate a high definition map for use in driving vehicles, for example, for guiding autonomous vehicles. A pose graph is built from the collected data, each pose representing location and orientation of a vehicle. The pose graph is optimized to minimize constraints between poses. Points associated with surface are assigned a confidence measure determined using a measure of hardness/softness of the surface. A machine-learning-based result filter detects bad alignment results and prevents them from being entered in the subsequent global pose optimization. The alignment framework is parallelizable for execution using a parallel/distributed architecture. Alignment hot spots are detected for further verification and improvement. The system supports incremental updates, thereby allowing refinements of sub-graphs for incrementally improving the high-definition map for keeping it up to date.Type: GrantFiled: March 21, 2022Date of Patent: February 11, 2025Assignee: NVIDIA CORPORATIONInventors: Chen Chen, Mark Damon Wheeler, Liang Zou
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Patent number: 12223429Abstract: In various examples, a two-dimensional (2D) and three-dimensional (3D) deep neural network (DNN) is implemented to fuse 2D and 3D object detection results for classifying objects. For example, regions of interest (ROIs) and/or bounding shapes corresponding thereto may be determined using one or more region proposal networks (RPNs)—such as an image-based RPN and/or a depth-based RPN. Each ROI may be extended into a frustum in 3D world-space, and a point cloud may be filtered to include only points from within the frustum. The remaining points may be voxelated to generate a volume in 3D world space, and the volume may be applied to a 3D DNN to generate one or more vectors. The one or more vectors, in addition to one or more additional vectors generated using a 2D DNN processing image data, may be applied to a classifier network to generate a classification for an object.Type: GrantFiled: December 6, 2023Date of Patent: February 11, 2025Assignee: NVIDIA CorporationInventors: Innfarn Yoo, Rohit Taneja
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Publication number: 20250045980Abstract: Aspects of this technical solution can obtain, according to a plurality of cameras oriented toward the surface of a three-dimensional (3D) model having a surface including a two-dimensional (2D) texture model, input according to corresponding views from the plurality of cameras of the 2D texture model on the surface of the 3D model, and generate, according to the input and according to a model configured to generate a two-dimensional (2D) image, an output including a 2D texture for the 3D model, the output responsive to receiving an indication of the 3D model and the 2D texture.Type: ApplicationFiled: July 31, 2023Publication date: February 6, 2025Applicant: NVIDIA CorporationInventors: Tianshi CAO, Kangxue YIN, Nicholas Mark Worth SHARP, Karsten Julian KREIS, Sanja FIDLER
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Publication number: 20250045952Abstract: In various examples, systems and methods are disclosed relating to real-time multiview map generation using neural networks. A system can receive sensors images of an environment, such as images from one or more camera, RADAR, LIDAR, and/or ultrasound sensors. The system can process the sensor images using one or more neural networks, such as neural networks implementing attention structures, to detect features in the environment such as lane lines, lane dividers, wait lines, or boundaries. The system can represent the features in various views, including top-down/bird's eye view representations. The system can provide the representations for operations including map generation, map updating, perception, and object detection.Type: ApplicationFiled: August 1, 2023Publication date: February 6, 2025Applicant: NVIDIA CorporationInventors: Alexander Popov, Nikolai Smolyanskiy, Ruchita Bhargava, Ibrahim Eden, Amala Sanjay Deshmukh, Ryan Oldja, Ke Chen, Sai Krishnan Chandrasekar, Minwoo Park
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Publication number: 20250048532Abstract: A circuit board includes chip die mounted on a three dimensional rectangular structure, a three dimensional triangular prism structure, or a combination thereof. A ball grid array for the chip die mounted on any such three dimensional structure is interposed between the three dimensional structure and the circuit board itself.Type: ApplicationFiled: October 18, 2024Publication date: February 6, 2025Applicant: NVIDIA Corp.Inventors: Joey Cai, Tiger Yan, Zhu Hao, Yi Dinghai
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Patent number: 12216969Abstract: Apparatuses, systems, and techniques apply to a force-based (e.g., primal) formulation for object simulation. In at least one embodiment, updates to the force-based formulation is determined by solving for constraints that are to be satisfied when simulating rigid bodies (e.g., contact rich scenarios).Type: GrantFiled: September 4, 2020Date of Patent: February 4, 2025Assignee: NVIDIA CorporationInventors: Miles Macklin, Matthias Mueller-Fischer, Nuttapong Chentanez, Stefan Jeschke, Tae-Yong Kim