Patents Assigned to NVidia
  • Patent number: 11941873
    Abstract: In various examples, sensor data may be received that represents a field of view of a sensor of a vehicle located in a physical environment. The sensor data may be applied to a machine learning model that computes both a set of boundary points that correspond to a boundary dividing drivable free-space from non-drivable space in the physical environment and class labels for boundary points of the set of boundary points that correspond to the boundary. Locations within the physical environment may be determined from the set of boundary points represented by the sensor data, and the vehicle may be controlled through the physical environment within the drivable free-space using the locations and the class labels.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: March 26, 2024
    Assignee: NVIDIA Corporation
    Inventors: Mansi Rankawat, Jian Yao, Dong Zhang, Chia-Chih Chen
  • Patent number: 11941899
    Abstract: Apparatuses, systems, and techniques generate poses of an object based on image data of the object obtained from a first viewpoint of the object and a second viewpoint of the object. The poses can be evaluated to determine a portion of the image data usable by an estimator to generate a pose of the object.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: March 26, 2024
    Assignee: NVIDIA Corporation
    Inventors: Jonathan Tremblay, Fabio Tozeto Ramos, Yuke Zhu, Anima Anandkumar, Guanya Shi
  • Patent number: 11941745
    Abstract: Disclosed approaches may leverage the actual spatial and reflective properties of a virtual environment—such as the size, shape, and orientation of a bidirectional reflectance distribution function (BRDF) lobe of a light path and its position relative to a reflection surface, a virtual screen, and a virtual camera—to produce, for a pixel, an anisotropic kernel filter having dimensions and weights that accurately reflect the spatial characteristics of the virtual environment as well as the reflective properties of the surface. In order to accomplish this, geometry may be computed that corresponds to a projection of a reflection of the BRDF lobe below the surface along a view vector to the pixel. Using this approach, the dimensions of the anisotropic filter kernel may correspond to the BRDF lobe to accurately reflect the spatial characteristics of the virtual environment as well as the reflective properties of the surface.
    Type: Grant
    Filed: June 28, 2022
    Date of Patent: March 26, 2024
    Assignee: NVIDIA Corporation
    Inventors: Shiqiu Liu, Christopher Ryan Wyman, Jon Hasselgren, Jacob Munkberg, Ignacio Llamas
  • Patent number: 11938406
    Abstract: In various examples, compute resources may be allocated for highlight generation in cloud gaming systems. Systems and methods are disclosed that distribute, between and among various devices, processing including user interface generation and overlay, analysis of game streams for actionable events, generation of highlights, storage of highlights, and sharing of highlights. The distribution of processing or compute resources within the cloud gaming system may be dependent on system information of various devices and/or networks. Recordings, snapshots, and/or other highlights may be generated within the cloud gaming system using the determined distribution of compute resources.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: March 26, 2024
    Assignee: NVIDIA Corporation
    Inventors: Stephen Holmes, Pierre Gervais
  • Patent number: 11941719
    Abstract: Various embodiments enable a robot, or other autonomous or semi-autonomous device or system, to receive data involving the performance of a task in the physical world. The data can be provided as input to a perception network to infer a set of percepts about the task, which can correspond to relationships between objects observed during the performance. The percepts can be provided as input to a plan generation network, which can infer a set of actions as part of a plan. Each action can correspond to one of the observed relationships. The plan can be reviewed and any corrections made, either manually or through another demonstration of the task. Once the plan is verified as correct, the plan (and any related data) can be provided as input to an execution network that can infer instructions to cause the robot, and/or another robot, to perform the task.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: March 26, 2024
    Assignee: NVIDIA Corporation
    Inventors: Jonathan Tremblay, Stan Birchfield, Stephen Tyree, Thang To, Jan Kautz, Artem Molchanov
  • Patent number: 11941743
    Abstract: A system and method for generating a set of samples stratified across two-dimensional elementary intervals of a two-dimensional space is disclosed within the application. A computer-implemented technique for generating the set of samples includes selecting an elementary interval associated with a stratification of the two-dimensional space, initializing at least one data structure that indicates valid regions within the elementary interface based on other samples previously placed within the two-dimensional space, and generating a sample in a valid region of the elementary interval utilizing the at least one data structure to identify the valid region prior to generating the sample. In some embodiments, the data structures comprise a pair of binary trees. The process can be repeated for each elementary interval of a selected stratification to generate the set of stratified two-dimensional samples.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: March 26, 2024
    Assignee: NVIDIA Corporation
    Inventor: Matthew Milton Pharr
  • Patent number: 11941819
    Abstract: A neural network may be used to determine corner points of a skewed polygon (e.g., as displacement values to anchor box corner points) that accurately delineate a region in an image that defines a parking space. Further, the neural network may output confidence values predicting likelihoods that corner points of an anchor box correspond to an entrance to the parking spot. The confidence values may be used to select a subset of the corner points of the anchor box and/or skewed polygon in order to define the entrance to the parking spot. A minimum aggregate distance between corner points of a skewed polygon predicted using the CNN(s) and ground truth corner points of a parking spot may be used simplify a determination as to whether an anchor box should be used as a positive sample for training.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: March 26, 2024
    Assignee: NVIDIA Corporation
    Inventors: Dongwoo Lee, Junghyun Kwon, Sangmin Oh, Wenchao Zheng, Hae-Jong Seo, David Nister, Berta Rodriguez Hervas
  • Patent number: 11941887
    Abstract: The present disclosure provides various approaches for smart area monitoring suitable for parking garages or other areas. These approaches may include ROI-based occupancy detection to determine whether particular parking spots are occupied by leveraging image data from image sensors, such as cameras. These approaches may also include multi-sensor object tracking using multiple sensors that are distributed across an area that leverage both image data and spatial information regarding the area, to provide precise object tracking across the sensors. Further approaches relate to various architectures and configurations for smart area monitoring systems, as well as visualization and processing techniques. For example, as opposed to presenting video of an area captured by cameras, 3D renderings may be generated and played from metadata extracted from sensors around the area.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: March 26, 2024
    Assignee: NVIDIA Corporation
    Inventors: Parthasarathy Sriram, Ratnesh Kumar, Farzin Aghdasi, Arman Toorians, Milind Naphade, Sujit Biswas, Vinay Kolar, Bhanu Pisupati, Aaron Bartholomew
  • Publication number: 20240095995
    Abstract: Techniques applicable to a ray tracing hardware accelerator for traversing a hierarchical acceleration structure with reduced false positive ray intersections are disclosed. The reduction of false positives may be based upon one or more of selectively performing a secondary higher precision intersection test for a bounding volume, identifying and culling bounding volumes that degenerate to a point, and parametrically clipping rays that exceed certain configured distance thresholds.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Applicant: NVIDIA Corporation
    Inventors: Gregory MUTHLER, John BURGESS, Magnus ANDERSSON, Ian KWONG, Edward BIDDULPH
  • Publication number: 20240094291
    Abstract: A circuit for improving control over asynchronous signal crossings during circuit scan tests includes multiple scan registers and a decoder configured to translate a combined output of the scan registers into multiple one-hot controls to the local clock gates of scan registers disposed in multiple different clock domains. Programmable registers are provided to selectively enable and disable the local clock gates of the different clock domains.
    Type: Application
    Filed: September 16, 2022
    Publication date: March 21, 2024
    Applicant: NVIDIA Corp.
    Inventors: Mahmut Yilmaz, Vinod Pagalone, Munish Aggarwal, Doochul Shin
  • Patent number: 11937028
    Abstract: Configurations for rack connection systems are disclosed. In at least one embodiment, installation locations for one or more cables are determined and one or more indicators corresponding to installation locations are activated.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: March 19, 2024
    Assignee: NVIDIA Corporation
    Inventors: Ryan Albright, William Andrew Mecham, Benjamin Goska, Aaron Richard Carkin, William Ryan Weese, Michael Thompson
  • Patent number: 11934311
    Abstract: Various embodiments include a system for managing cache memory in a computing system. The system includes a sectored cache memory that provides a mechanism for sharing sectors in a cache line among multiple cache line allocations. Traditionally, different cache line allocations are assigned to different cache lines in the cache memory. Further, cache line allocations may not use all of the sectors of the cache line, leading to low utilization of the cache memory. With the present techniques, multiple cache lines share the same cache line, leading to improved cache memory utilization relative to prior techniques. Further, sectors of cache allocations can be assigned to reduce data bank conflicts when accessing cache memory. Reducing such data bank conflicts can result in improved memory access performance, even when cache lines are shared with multiple allocations.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: March 19, 2024
    Assignee: NVIDIA CORPORATION
    Inventors: Michael Fetterman, Steven James Heinrich, Shirish Gadre
  • Patent number: 11931909
    Abstract: Apparatuses, systems, and techniques generate poses of an object based on data of the object observed from a first viewpoint and a second viewpoint. The poses can be evaluated to determine a portion of the data usable by an estimator to generate a pose of the object.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: March 19, 2024
    Assignee: NVIDIA Corporation
    Inventors: Jonathan Tremblay, Fabio Tozeto Ramos, Yuke Zhu, Anima Anandkumar, Guanya Shi
  • Patent number: 11934959
    Abstract: Apparatuses, systems, and techniques are presented to synthesize consistent images or video. In at least one embodiment, one or more neural networks are used to generate one or more second images based, at least in part, on one or more point cloud representations of one or more first images.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: March 19, 2024
    Assignee: NVIDIA CORPORATION
    Inventors: Arun Mallya, Ting-Chun Wang, Ming-Yu Liu, Karan Sapra
  • Patent number: 11934872
    Abstract: A system is provided for monitoring and controlling program flow in an event-triggered system. A program (e.g., application, algorithm, routine, etc.) may be organized into operational units (e.g., nodes executed by one or more processors), each of which tasked with executing one or more respective events (e.g., tasks) within the larger program. At least some of the events of the larger program may be successively executed in a flow, one after another, using triggers sent directly from one node to the next. In addition, the system of the present disclosure may include a manager that may exchange communications with the nodes to monitor or assess a status of the system (e.g., determine when a node has completed an event) or to control or trigger a node to initiate an event.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: March 19, 2024
    Assignee: NVIDIA Corporation
    Inventors: Peter Alexander Boonstoppel, Michael Cox, Daniel Perrin
  • Patent number: 11934567
    Abstract: A host may use address translation to convert virtual addresses to physical addresses for endpoints, which may then submit memory access requests for physical addresses. The host may incorporate the physical address and a signature of the physical address generated using a private key into a translated address field of a response to a translation request. An endpoint may treat the combination as a translated address by storing it in an entry of a translation cache, and accessing the entry for inclusion in a memory access request. The host may generate a signature of the translated address from the request using the private key, with the result being compared to the signature from the request. The memory access request may be verified when the compared values match, and the memory access may be performed using the translated address.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: March 19, 2024
    Assignee: NVIDIA Corporation
    Inventors: Jonathon Evans, Kaushal Agarwal
  • Patent number: 11934867
    Abstract: Warp sharding techniques to switch execution between divergent shards on instructions that trigger a long stall, thereby interleaving execution between diverged threads within a warp instead of across warps. The technique may be applied to mitigate pipeline stalls in applications with low warp occupancy and high divergence. Warp data cache locality may also be improved by concentrating memory accesses within a warp rather than spreading them across warps.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: March 19, 2024
    Assignee: NVIDIA CORP.
    Inventors: Sana Damani, Mark Stephenson, Ram Rangan, Daniel Robert Johnson, Rishkul Kulkarni
  • Patent number: 11934242
    Abstract: Provided, in one aspect, is a data center. The data center, in this aspect, includes a data center enclosure, the data center enclosure designed for a given supply of power (Ps). The data center, according to this aspect, further includes N independent coolable clusters of data center racks located within the data center enclosure, wherein N is at least two, and further wherein the N independent coolable clusters each have an ostensible power demand (Pos) approximately equal to Ps/N, and each of the N independent coolable clusters has a respective actual power demand (Pac) adjustable at, above or below the ostensible power demand (Pos).
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: March 19, 2024
    Assignee: Nvidia Corporation
    Inventor: Alex R. Naderi
  • Patent number: 11935179
    Abstract: A fully-connected neural network may be configured for execution by a processor as a fully-fused neural network by limiting slow global memory accesses to reading and writing inputs to and outputs from the fully-connected neural network. The computational cost of fully-connected neural networks scale quadratically with its width, whereas its memory traffic scales linearly. Modern graphics processing units typically have much greater computational throughput compared with memory bandwidth, so that for narrow, fully-connected neural networks, the linear memory traffic is the bottleneck. The key to improving performance of the fully-connected neural network is to minimize traffic to slow “global” memory (off-chip memory and high-level caches) and to fully utilize fast on-chip memory (low-level caches, “shared” memory, and registers), which is achieved by the fully-fused approach.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: March 19, 2024
    Assignee: NVIDIA Corporation
    Inventors: Thomas Müller, Nikolaus Binder, Fabrice Pierre Armand Rousselle, Jan Novák, Alexander Georg Keller
  • Patent number: 11935177
    Abstract: Disclosed are apparatuses, systems, and techniques to render images with global illumination using efficient ray tracing, light source identification, and reservoir resampling that deploys temporal and spatial reservoirs.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: March 19, 2024
    Assignee: Nvidia Corporation
    Inventors: Yaobin Ouyang, Nan Lin, Jacopo Pantaleoni, Markus Kettunen, Shiqiu Liu