Patents Assigned to NVidia
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Patent number: 11055097Abstract: One embodiment of the present invention includes techniques to decrease power consumption by reducing the number of redundant operations performed. In operation, a streamlining multiprocessor (SM) identifies uniform groups of threads that, when executed, apply the same deterministic operation to uniform sets of input operands. Within each uniform group of threads, the SM designates one thread as the anchor thread. The SM disables execution units assigned to all of the threads except the anchor thread. The anchor execution unit, assigned to the anchor thread, executes the operation on the uniform set of input operands. Subsequently, the SM sets the outputs of the non-anchor threads included in the uniform group of threads to equal the value of the anchor execution unit output.Type: GrantFiled: October 8, 2013Date of Patent: July 6, 2021Assignee: NVIDIA CorporationInventors: Gary M. Tarolli, John H. Edmondson, John Matthew Burgess, Robert Ohannessian
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Patent number: 11055381Abstract: Sampling a function is used for many applications, such as rendering images. The challenge is how to select the best samples to minimize computations and produce accurate results. An alternative is to use a larger number of samples that may not be carefully selected in an attempt to increase accuracy. For a function that is an integral, such as functions used to render images, a sample distribution may be computed by inverting the integral. Unfortunately, for many integrals, it is neither easy nor practical to compute the inverted integral. Instead, warp functions may be combined to provide a sample distribution that accurately approximates the factors of the product being integrated. Each warp function approximates an inverted term of the product while accounting for the effects of warp functions approximating other factors in the product. The selected warp functions are customized or “fitted” to implement importance sampling for the approximated product.Type: GrantFiled: June 12, 2020Date of Patent: July 6, 2021Assignee: NVIDIA CorporationInventors: David Augustus Hart, Matthew Milton Pharr, Thomas Müller, Ward Lopes, Morgan McGuire, Peter Schuyler Shirley
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Patent number: 11055253Abstract: This disclosure provides a method that allows connector pins of a USB-C connector to be dynamically repurposed between low bandwidth USB2 traffic and high bandwidth USB3 traffic. USB-C devices can negotiate the use of these pins for a dynamic transition to another function or functions. The pins can be the four center connector pins of a USB-C connection, pins A6, A7, B6, B7, that are originally designated as USB 2.0 differential pairs Changing the function of the pins provides flexibility for communicating using USB-C connectors. For example, the disclosed method/device/system can be used to support high-resolution cameras and sensors in high-resolution virtual reality headsets via a single USB-C connection instead of a user having to connect multiple cables.Type: GrantFiled: October 17, 2018Date of Patent: July 6, 2021Assignee: Nvidia CorporationInventors: Luc Bisson, Rambod Jacoby, Mark Overby
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Patent number: 11048321Abstract: Digital low-dropout micro voltage regulator configured to accept an external voltage and produce a regulated voltage. All active devices of the voltage regulator are digital devices. All signals of the voltage regulator, except the first voltage and the regulated voltage, may be characterized as digital signals. Some active devices of the voltage regulator may be physically separated from other active devices of the voltage regulator by active devices of non-voltage regulator circuitry.Type: GrantFiled: June 1, 2018Date of Patent: June 29, 2021Assignee: NVIDIA CORPORATIONInventors: Siddharth Saxena, Tezaswi Raja, Fei Li, Wen Yueh
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Patent number: 11049018Abstract: A method, computer readable medium, and system are disclosed for visual sequence learning using neural networks. The method includes the steps of replacing a non-recurrent layer within a trained convolutional neural network model with a recurrent layer to produce a visual sequence learning neural network model and transforming feedforward weights for the non-recurrent layer into input-to-hidden weights of the recurrent layer to produce a transformed recurrent layer. The method also includes the steps of setting hidden-to-hidden weights of the recurrent layer to initial values and processing video image data by the visual sequence learning neural network model to generate classification or regression output data.Type: GrantFiled: January 25, 2018Date of Patent: June 29, 2021Assignee: NVIDIA CorporationInventors: Xiaodong Yang, Pavlo Molchanov, Jan Kautz
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Patent number: 11043172Abstract: A display controller progressively updates LEDs and LCD pixels in scanline order as portions of an image are scanned into a frame buffer. The display controller analyzes a first portion of the image that includes a first pixel value associated with a first LCD pixel. The display controller identifies a first LED that contributes luminance to the first LCD pixel and determines an LED current setting for the LED based on the first pixel value. The display controller then identifies a second LCD pixel that resides above the first LED and is associated with a second pixel value. The display controller configures the second LCD pixel based on the second pixel value and luminance contributions received at the second LCD pixel. Accordingly, the display controller need not wait for the entire image to be scanned into the frame buffer before initiating display of the image.Type: GrantFiled: February 5, 2019Date of Patent: June 22, 2021Assignee: NVIDIA CorporationInventors: Gerrit Ary Slavenburg, Robert Jan Schutten, Jens Roever, Tom J. Verbeure
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Patent number: 11043028Abstract: A method, computer readable medium, and system are disclosed for overlaying a cell onto a polygon meshlet. The polygon meshlet may include a grouping of multiple geometric shapes such as triangles, and the cell may include a square-shaped boundary. Additionally, every polygon (e.g., a triangle or other geometric shape) within the polygon meshlet that has at least one edge fully inside the cell is removed to create an intermediate meshlet. A selected vertex is determined from all vertices (e.g., line intersections) of the intermediate meshlet that are located within the cell, based on one or more criteria, and all the vertices of the intermediate meshlet that are located within the cell are replaced with the selected vertex to create a modified meshlet. The modified meshlet is then rendered (e.g., as part of a process to generate a scene to be viewed).Type: GrantFiled: November 2, 2018Date of Patent: June 22, 2021Assignee: NVIDIA CORPORATIONInventor: Holger Heinrich Gruen
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Patent number: 11042163Abstract: In various examples, a trigger signal may be received that is indicative of a vehicle maneuver to be performed by a vehicle. A recommended vehicle trajectory for the vehicle maneuver may be determined in response to the trigger signal being received. To determine the recommended vehicle trajectory, sensor data may be received that represents a field of view of at least one sensor of the vehicle. A value of a control input and the sensor data may then be applied to a machine learning model(s) and the machine learning model(s) may compute output data that includes vehicle control data that represents the recommended vehicle trajectory for the vehicle through at least a portion of the vehicle maneuver. The vehicle control data may then be sent to a control component of the vehicle to cause the vehicle to be controlled according to the vehicle control data.Type: GrantFiled: January 7, 2019Date of Patent: June 22, 2021Assignee: NVIDIA CorporationInventors: Chenyi Chen, Artem Provodin, Urs Muller
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Patent number: 11037051Abstract: Planar regions in three-dimensional scenes offer important geometric cues in a variety of three-dimensional perception tasks such as scene understanding, scene reconstruction, and robot navigation. Image analysis to detect planar regions can be performed by a deep learning architecture that includes a number of neural networks configured to estimate parameters for the planar regions. The neural networks process an image to detect an arbitrary number of plane objects in the image. Each plane object is associated with a number of estimated parameters including bounding box parameters, plane normal parameters, and a segmentation mask. Global parameters for the image, including a depth map, can also be estimated by one of the neural networks. Then, a segmentation refinement network jointly optimizes (i.e., refines) the segmentation masks for each instance of the plane objects and combines the refined segmentation masks to generate an aggregate segmentation mask for the image.Type: GrantFiled: September 10, 2019Date of Patent: June 15, 2021Assignee: NVIDIA CorporationInventors: Kihwan Kim, Jinwei Gu, Chen Liu, Jan Kautz
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Patent number: 11037338Abstract: This disclosure introduces an approach that includes techniques for determining an optimal weighted execution sequence of available reconstruction algorithms using a multi-processor unit. The introduced approach includes executing a series of optimal weighted execution sequence candidates on a representative slice of the image data and comparing their results to select one of the candidates as the optimal weighted execution sequence.Type: GrantFiled: April 5, 2019Date of Patent: June 15, 2021Assignee: Nvidia CorporationInventor: Shekhar Dwivedi
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Patent number: 11039092Abstract: To support sparse scanout of an image sensor, an image data protocol such as the MIPI CSI protocol is extended with support for pixel coordinates in long packets. The receiver uses these to compute where in memory these pixels should be stored or where on a display they should be displayed. Truly sparse scanout is supported for any arbitrarily shaped image areas including for example elliptical readout for fisheye lenses. These techniques save MIPI and serializer/deserializer bandwidth in automotive and other applications, allowing for more cameras per vehicle or other host. Such techniques can be implemented in a way that is compatible with prior MIPI standardized approaches.Type: GrantFiled: November 9, 2018Date of Patent: June 15, 2021Assignee: NVIDIA CorporationInventor: Joshua Wise
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Patent number: 11038800Abstract: An endpoint in a network may make posted or non-posted write requests to another endpoint in the network. For a non-posted write request, the target endpoint provides a response to the requesting endpoint indicating that the write request has been serviced. For a posted write request, the target endpoint does not provide such an acknowledgment. Hence, posted write requests have lower overhead, but they suffer from potential synchronization and resiliency issues. While non-posted write requests do not have those issues, they cause increased load on the network because such requests require the target endpoint to acknowledge each write request. Introduced herein is a network operation technique that uses non-posted transactions while maintaining a load overhead of the network as a manageable level. The introduced technique reduces the load overhead of the non-posted write requests by collapsing and reducing a number of the responses.Type: GrantFiled: August 28, 2019Date of Patent: June 15, 2021Assignee: Nvidia CorporationInventors: Glenn Dearth, Mark Hummel, Jonathan Owen, Mike Osborn, John Wortman, Rich Reeves
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Patent number: 11027199Abstract: Embodiments of the claimed subject matter provide systems and methods for configuring and connecting a controller to a game streaming service. The system includes a plurality of input controls and a network controller configured for communicating with a game streaming service. The system further includes a processor coupled to the plurality of input controls and the network controller. The processor is configured communicate with the game streaming service to login to a game streaming service account and communicate input from the plurality of controls to the game streaming service. The system further includes a power source configured to provide power to the plurality of input controls, the network controller, and the processor.Type: GrantFiled: February 10, 2020Date of Patent: June 8, 2021Assignee: Nvidia CorporationInventor: Stephen Holmes
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Patent number: 11030968Abstract: In various examples, images rendered by a processor—such as a graphics processing unit (GPU)—may be scanned out of memory in a middle-out scan order. Various architectures for liquid crystal displays (LCDs) may be implemented to support middle-out scanning, such as dual-panel architectures, ping-pong architectures, and architectures that support both top-down scan order and middle-out scan order. As a result, display latency within the system may be reduced, thereby increasing performance of the system—especially for high-performance applications such as gaming.Type: GrantFiled: April 9, 2020Date of Patent: June 8, 2021Assignee: NVIDIA CorporationInventors: Gerrit Slavenburg, Tom J. Verbeure
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Patent number: 11023732Abstract: In various examples, potentially highlight-worthy video clips are identified from a gameplay session that a gamer might then selectively share or store for later viewing. The video clips may be identified in an unsupervised manner based on analyzing game data for durations of predicted interest. A classification model may be trained in an unsupervised manner to classify those video clips without requiring manual labeling of game-specific image or audio data. The gamer can select the video clips as highlights (e.g., to share on social media, store in a highlight reel, etc.). The classification model may be updated and improved based on new video clips, such as by creating new video-clip classes.Type: GrantFiled: July 2, 2019Date of Patent: June 1, 2021Assignee: NVIDIA CorporationInventor: Prabindh Sundareson
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Publication number: 20210158127Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.Type: ApplicationFiled: April 27, 2020Publication date: May 27, 2021Applicant: NVIDIA Corp.Inventors: Haoxing Ren, George Kokai, Ting Ku, Walker Joseph Turner
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Publication number: 20210158155Abstract: A graph neural network for average power estimation of netlists is trained with register toggle rates over a power window from an RTL simulation and gate level netlists as input features. Combinational gate toggle rates are applied as labels. The trained graph neural network is then applied to infer combinational gate toggle rates over a different power window of interest and/or different netlist.Type: ApplicationFiled: August 13, 2020Publication date: May 27, 2021Applicant: NVIDIA Corp.Inventors: Yanqing Zhang, Haoxing Ren, Brucek Khailany
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Patent number: 11018909Abstract: A receiver receives communications over a communication channel, which may distort an incoming communication signal. In order to counter this distortion, the frequency response of the receiver is manipulated by adjusting several frequency response parameters. Each frequency response parameter controls at least a portion of the frequency response of the receiver. The optimal values for the frequency response parameters are determined by modifying an initial set of values for the frequency response parameters through one or more of stochastic hill climbing operations until a performance metric associated with the receiver reaches a local maximum. The modified values are displaced through one or more mutation operations. The stochastic hill climbing operations may subsequently be performed on the mutated values to generate the final values for the frequency response parameters.Type: GrantFiled: August 13, 2020Date of Patent: May 25, 2021Assignee: NVIDIA CorporationInventors: Vishnu Balan, Mohammed Mobin, Rohit Rathi, Dai Dai
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Patent number: 11016802Abstract: In various embodiments, an ordered atomic operation enables a parallel processing subsystem to executes an atomic operation associated with a memory location in a specified order relative to other ordered atomic operations associated with the memory location. A level 2 (L2) cache slice includes an atomic processing circuit and a content-addressable memory (CAM). The CAM stores an ordered atomic operation specifying at least a memory address, an atomic operation, and an ordering number. In operation, the atomic processing circuit performs a look-up operation on the CAM, where the look-up operation specifies the memory address. After the atomic processing circuit determines that the ordering number is equal to a current ordering number associated with the memory address, the atomic processing circuit executes the atomic operation and returns the result to a processor executing an algorithm.Type: GrantFiled: January 26, 2018Date of Patent: May 25, 2021Assignee: NVIDIA CorporationInventors: Ziyad Hakura, Olivier Giroux, Wishwesh Gandhi
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Patent number: 11017556Abstract: Iterative prediction systems and methods for the task of action detection process an inputted sequence of video frames to generate an output of both action tubes and respective action labels, wherein the action tubes comprise a sequence of bounding boxes on each video frame. An iterative predictor processes large offsets between the bounding boxes and the ground-truth.Type: GrantFiled: October 4, 2018Date of Patent: May 25, 2021Assignee: NVIDIA CorporationInventors: Xiaodong Yang, Xitong Yang, Fanyi Xiao, Ming-Yu Liu, Jan Kautz