Abstract: Novel solutions are provided for consistent Quality of Service in cloud gaming system that adaptively and dynamically compensate for poor network conditions by moderating rendered frame rates using frame rate capping to optimize for network latency savings (or surplus). In further embodiments, the encoding/sent frame rate to the client can also be managed in addition, or as an alternative to capping the rendered frame rates. The claimed embodiments not only maintain a constant Quality of Service (QoS) for the user, but may also be employed to leverage higher-performing networks to reduce operational costs.

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

Abstract: The present disclosure is directed to a method to increase virtual machine density on a server system through adaptive rendering by dynamically determining when to shift video rendering tasks between the server system and a client computing device. In another embodiment, the adaptive rendering, using various parameters, can select one or more encoding and compression algorithms to use to prepare and process the video for transmission to the client computing device. In another embodiment, a video rendering system is disclosed that can adaptively alter how and where a video is rendered, encoded, and compressed.

Abstract: Testing packaged integrated circuit (IC) devices is difficult and time consuming. When multiple devices (dies) are packaged to produce a SiP (system in package) the devices should be tested for defects that may be introduced during the packaging process. With limited access to the inputs and outputs of the devices, test times increase compared with testing the devices before they are packaged. A CoWoS (chip on wafer on substrate) SiP includes a logic device and a memory device and has interfaces between the logic device and memory device that cannot be directly accessed at a package ball. Test programs are concurrently executed by the logic device and the memory device to reduce testing time. Each memory device includes a BIST (built-in self-test) module that is initialized and executes the memory test program while the one or more modules within the logic device are tested.

Abstract: Embodiments of the present invention provide a novel method and discretization for animating water waves. The approaches disclosed combine the flexibility of a numerical approach to wave simulation with the stability and visual detail provided by a spectrum-based approach to provide Eulerian methods for simulating large-scale oceans with highly detailed wave features. A graphics processing unit stores a one-dimensional texture referred to as a wave profile buffer that stores pre-computed results at a number of discrete sample points for performing wave height evaluation. The water surface is rendered according to water height values computed using the wave profile, accounting for advection, spatial diffusion, angular diffusion, boundary reflections, and dissipation.

Abstract: A water surface mesh is determined for a scene to be rendered. This water surface mesh includes a grouping of geometric shapes such as triangles that represents the surface of the water. This water surface mesh is then used to create a refracted or reflected mesh. The refracted or reflected mesh shows an effect produced by the water surface's refraction or reflection of light. The relationship between the water surface mesh and the refracted or reflected mesh is then used to determine how to illuminate elements within the scene. This eliminates some previously necessary steps during rendering, and enables an accurate depiction of caustics within a scene that can be performed in real-time.

Abstract: This disclosure relates to a receiver comprising a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.

Abstract: A ray (e.g., a traced path of light, etc.) is generated from an originating pixel within a scene being rendered. Additionally, one or more shadow map lookups are performed for the originating pixel to estimate an intersection of the ray with alpha-tested geometry within the scene. A shadow map stores the distance of geometry as seen from the point of view of the light, and alpha-tested geometry includes objects within the scene being rendered that have a determined texture and opacity. Further, the one or more shadow map lookups are performed to determine a visibility value for the pixel (e.g., that identifies whether the originating pixel is in a shadow) and a distance value for the pixel (e.g., that identifies how far the pixel is from the light). Further still, the visibility value and the distance value for the pixel are passed to a denoiser.

Abstract: A hierarchy of interconnected memory retention (MR) circuits detect a clock gating mode being entered at any level of an integrated circuit. In response, the hierarchy automatically transitions memory at the clock gated level and all levels below the clock-gated level from a normal operating state to a memory retention state. When a memory transitions from a normal operating state to a memory retention state, the memory transitions from a higher power state (corresponding to the normal operating state) to a lower power state (corresponding to the memory retention state). Thus, in addition to the dynamic power savings caused by the clock gating mode, the hierarchy of MR circuits automatically transitions the memory modules at the clock gated level and all levels below the clock gated level to a lower power state. As a result, the leakage power consumption of the corresponding memory modules is reduced relative to prior approaches.

Abstract: Users often desire to capture certain images from an application. For example, gamers can capture displayed images from a game to show they obtained a skill level within the game or simply to capture a particular scene within the game. Existing methods of capturing images can result in low-resolution images due to limitations of the display device providing the images. This disclosure provides a method of capturing higher resolution images from source images. Techniques are also disclosed to reduce the storage size associated with the higher resolution images. Through capturing low-resolution versions of the same source images, image effects can be captured and applied to the higher resolution images where those image effects may be altered or missing. Frequency spectrum combination can be used to combine the low-resolution image data and the higher resolution image data. The higher resolution images can be processed using a segmentation scheme, such as tiling, without reducing or limiting the image effects.

Abstract: Aspects of the present invention are directed to computer-implemented techniques for performing data compression and conversion between data formats of varying degrees of precision, and more particularly for improving the inferencing (application) of artificial neural networks using a reduced precision (e.g., INT8) data format. Embodiments of the present invention generate candidate conversions of data output, then employ a relative measure of quality to identify the candidate conversion with the greatest accuracy (i.e., least divergence from the original higher precision values). The representation can be then be used during inference to perform computations on the resulting output data.

Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data receiver front ends.

Abstract: A method, computer program product, and system perform computations using a sparse convolutional neural network accelerator. Compressed-sparse data is received for input to a processing element, wherein the compressed-sparse data encodes non-zero elements and corresponding multi-dimensional positions. The non-zero elements are processed in parallel by the processing element to produce a plurality of result values. The corresponding multi-dimensional positions are processed in parallel by the processing element to produce destination addresses for each result value in the plurality of result values. Each result value is transmitted to a destination accumulator associated with the destination address for the result value.

Abstract: In various examples, object fence corresponding to objects detected by an ego-vehicle may be used to determine overlap of the object fences with lanes on a driving surface. A lane mask may be generated corresponding to the lanes on the driving surface, and the object fences may be compared to the lanes of the lane mask to determine the overlap. Where an object fence is located in more than one lane, a boundary scoring approach may be used to determine a ratio of overlap of the boundary fence, and thus the object, with each of the lanes. The overlap with one or more lanes for each object may be used to determine lane assignments for the objects, and the lane assignments may be used by the ego-vehicle to determine a path or trajectory along the driving surface.

Abstract: In various examples, sensor data representative of an image of a field of view of a vehicle sensor may be received and the sensor data may be applied to a machine learning model. The machine learning model may compute a segmentation mask representative of portions of the image corresponding to lane markings of the driving surface of the vehicle. Analysis of the segmentation mask may be performed to determine lane marking types, and lane boundaries may be generated by performing curve fitting on the lane markings corresponding to each of the lane marking types. The data representative of the lane boundaries may then be sent to a component of the vehicle for use in navigating the vehicle through the driving surface.

Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.

Abstract: One aspect of the current disclosure provides a method for utilizing a plurality of memories associated with a plurality of devices in a computer system. The method includes: 1) receiving a data set for executing an application employing the devices; 2) determining whether the data set is larger than a storage capacity of any of the memories; and 3) when the data set is larger than the storage capacity of any of the memories, replicating a portion of the data set across the memories and distributing a remaining portion of the data set across at least some of the memories.

Abstract: Novel solutions are provided for consistent Quality of Service in cloud gaming system that adaptively and dynamically compensate for poor network conditions by moderating rendered frame rates using frame rate capping to optimize for network latency savings (or surplus). In further embodiments, the encoding/sent frame rate to the client can also be managed in addition, or as an alternative to capping the rendered frame rates. The claimed embodiments not only maintain a constant Quality of Service (QoS) for the user, but may also be employed to leverage higher-performing networks to reduce operational costs.

Abstract: The present disclosure is directed to a method to correct for visual artifacts in a virtual reality (VR) video image where there is significant motion of the video image as a result of user actions. A user may request that the video image be moved, such as a through motion detected through a VR device, i.e., turning the head, or through a request to an application, i.e., joystick feedback to a gaming application. The video image motion can cause stutter and jitter visual artifacts, when the video frame buffer uses a synchronization constraint, such as vertical synchronization (VSync). When the VSync is disabled, a tearing visual artifact can be present. This disclosure presents a frame buffer handling process that operates with VSync disabled. The process allows the display refresh rates to operate at higher frequencies, while correcting for significant motion of the video image, i.e., tearing, through shifting back certain pixels within the scanout frame buffer.

Abstract: This disclosure relates to an adder circuit. The adder circuit comprises an operand input and a second operand input to an XNOR cell. The XNOR cell may be configured to provide the operand input and the second operand input to both a NAND gate and a first OAI cell. A second OAI cell may transform the output of the XNOR cell into a carry out signal.