Patents Assigned to NVidia
  • Patent number: 10969740
    Abstract: A method for rendering a light field comprises projecting rays from a viewpoint positioned at a first side of a spatial light modulator (SLM) to a clipping plane positioned at an opposing side of the SLM to form an elemental view frustum within a three-dimensional scene and rendering objects within the elemental view frustum to generate components of a first elemental image for the first elemental region. The SLM may include a tiled array of non-overlapping elemental regions and a top edge and a bottom edge of a first elemental region of the non-overlapping elemental regions are intersected by the rays to form the elemental view frustum. Furthermore, the light field may include the first elemental image and additional elemental images corresponding to the array of elemental regions and each one of the additional elemental images is rendered using an additional elemental view frustum.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: April 6, 2021
    Assignee: NVIDIA Corporation
    Inventors: Liang Shi, Fu-Chung Huang, Ward Lopes
  • Patent number: 10964000
    Abstract: Systems and techniques for noise reduction in video are described. Example implementations provide improved motion-adaptive temporal or spatio-temporal noise reduction that use an improved blending of the current frame with previous frames. The improved blending may be particularly effective for processing video captured in noisy environments such as low-light and/or mobile environments. In some example implementations, the improved blending is based on more accurately distinguishing between pixel difference in adjacent images that are caused by motion rather than noise.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: March 30, 2021
    Assignee: NVIDIA Corporation
    Inventors: Seungseok Oh, Sean Pieper
  • Patent number: 10964034
    Abstract: Due to the factors such as lens distortion and camera misalignment, stereoscopic image pairs often contain vertical disparities. Introduced herein is a method and apparatus that determine and correct vertical disparities in stereoscopic image pairs using an optical flow map. Instead of discarding vertical motion vectors of the optical flow map, the introduced concept extracts and analyzes the vertical motion vectors from the optical flow map and vertically aligns the images using the vertical disparity determined from the vertical motion vectors. The introduced concept recognizes that although not apparent, vertical motion does exist in stereoscopic images and can be used to correct the vertical disparity in stereoscopic images.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: March 30, 2021
    Assignee: Nvidia Corporation
    Inventor: David Cook
  • Patent number: 10964061
    Abstract: A deep neural network (DNN) system learns a map representation for estimating a camera position and orientation (pose). The DNN is trained to learn a map representation corresponding to the environment, defining positions and attributes of structures, trees, walls, vehicles, etc. The DNN system learns a map representation that is versatile and performs well for many different environments (indoor, outdoor, natural, synthetic, etc.). The DNN system receives images of an environment captured by a camera (observations) and outputs an estimated camera pose within the environment. The estimated camera pose is used to perform camera localization, i.e., recover the three-dimensional (3D) position and orientation of a moving camera, which is a fundamental task in computer vision with a wide variety of applications in robot navigation, car localization for autonomous driving, device localization for mobile navigation, and augmented/virtual reality.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: March 30, 2021
    Assignee: NVIDIA Corporation
    Inventors: Jinwei Gu, Samarth Manoj Brahmbhatt, Kihwan Kim, Jan Kautz
  • Patent number: 10965440
    Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty cycle error, combined with a local offset value for each data lane, and is applied to data receiver front ends.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: March 30, 2021
    Assignee: NVIDIA Corp.
    Inventors: Xi Chen, Nikola Nedovic, Carl Thomas Gray, Stephen G Tell
  • Publication number: 20210088784
    Abstract: A gaze tracking system for use by the driver of a vehicle includes an opaque frame circumferentially enclosing a transparent field of view of the driver, light emitting diodes coupled to the opaque frame for emitting infrared light onto various regions of the driver's eye gazing through the transparent field of view, and diodes for sensing intensity of infrared light reflected off of various regions of the driver's eye.
    Type: Application
    Filed: September 20, 2019
    Publication date: March 25, 2021
    Applicant: Nvidia Corp.
    Inventors: Eric Whitmire, Kaan Aksit, Michael Stengel, Jan Kautz, David Luebke, Ben Boudaoud
  • Publication number: 20210089465
    Abstract: An addressing scheme in systems utilizing a number of operative memory slices in a last level cache that is not evenly divisible by a number of memory channels utilizes the operative slices exposes the full last level cache bandwidth and capacity to data processing logic in a high-performance graphics system.
    Type: Application
    Filed: September 25, 2019
    Publication date: March 25, 2021
    Applicant: NVIDIA Corp.
    Inventors: Prakash Bangalore Prabhakar, James M. Van Dyke, Kun Fang
  • Patent number: 10957651
    Abstract: A die package is disclosed through which power domains within the chip may be isolated by removing vias within the package substrate, rather than power gating. Multiple substrate options may be configured without specific vias. This eliminates the need to design power gating circuitry into the die, freeing up that die area for more functional logic. The solution allows the die package to retain the same pinout for use by PCB designers, regardless of which power domains are gated.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: March 23, 2021
    Assignee: NVIDIA Corp.
    Inventors: Don Templeton, Luke Young Chang, Narayan Kulshrestha
  • Patent number: 10957078
    Abstract: A raster unit is configured to generate different sample patterns for adjacent pixels within a given frame. In addition, the raster unit may adjust the sample patterns between frames. The raster unit includes an index unit that selects a sample pattern table for use with a current frame. For a given pixel, the index unit extracts a sample pattern from the selected sample pattern table. The extracted sample pattern is used to generate coverage information for the pixel. The coverage information for all pixels is then used to generate an image. The resultant image may then be filtered to reduce or remove artifacts induced by the changing of sample locations.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: March 23, 2021
    Assignee: NVIDIA Corporation
    Inventors: Yury Y. Uralsky, Jonah M. Alben, Ankan Banerjee, Gregory Massal, Thomas Petersen, Oleg Kuznetsov, Eric B. Lum, Prakshep Mehta
  • Patent number: 10957020
    Abstract: Embodiments of the present invention provide end-to-end frame time synchronization designed to improve smoothness for displaying images of 3D applications, such as PC gaming applications. Traditionally, an application that renders 3D graphics functions based on the assumption that the average render time will be used as the animation time for a given frame. When this condition is not met, and the render time for a frame does not match the average render time of prior frames, the frames are not captured or displayed at a consistent rate. This invention enables feedback to be provided to the rendering application for adjusting the animation times used to produce new frames, and a post-render queue is used to store completed frames for mitigating stutter and hitches. Flip control is used to sync the display of a rendered frame with the animation time used to generate the frame, thereby producing a smooth, consistent image.
    Type: Grant
    Filed: December 3, 2018
    Date of Patent: March 23, 2021
    Assignee: NVIDIA CORPORATION
    Inventors: Thomas Albert Petersen, Ankan Banerjee, Shishir Goyal, Sau Yan Keith Li, Lars Nordskog, Rouslan Dimitrov
  • Publication number: 20210083836
    Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data receiver front ends.
    Type: Application
    Filed: June 18, 2020
    Publication date: March 18, 2021
    Applicant: NVIDIA Corp.
    Inventors: Xi Chen, Nikola Nedovic, Carl Thomas Gray, Stephen G. Tell
  • Publication number: 20210083837
    Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty cycle error, combined with a local offset value for each data lane, and is applied to data receiver front ends.
    Type: Application
    Filed: July 13, 2020
    Publication date: March 18, 2021
    Applicant: NVIDIA Corp.
    Inventors: Xi Chen, Nikola Nedovic, Carl Thomas Gray, Stephen G Tell
  • Patent number: 10948985
    Abstract: Perceived clarity of an image presented by a display can be improved using an image stabilization technique to stabilize the image relative to a user's retina. During an illumination period, stabilization actuators are controlled to move a display panel or adjust optical components in the path of light associated with the image to shift the location of the image on the user's retina in response to head or eye movement detected by the system. In some embodiments, a display is configured to illuminate an image, and at least one stabilization actuator is configured to stabilize the image in a retina space associated with a user. Changes in the retina space can be detected by one or more sensors configured to detect a head position of the user and/or an orientation of the user's retina. The image is stabilized in retina space using the stabilization actuators.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: March 16, 2021
    Assignee: NVIDIA Corporation
    Inventors: Thomas Hastings Greer, Josef Bo Spjut, David Patrick Luebke
  • Patent number: 10946281
    Abstract: In various embodiments of the present disclosure, playstyle patterns of players are learned and used to generate virtual representations (“bots”) of users. Systems and methods are disclosed that use game session data (e.g., metadata) from a plurality of game sessions of a game to learn playstyle patterns of users, based on user inputs of the user in view of variables presented within the game sessions. The game session data is applied to one or more machine learning models to learn playstyle patterns of the user for the game, and associated with a user profile of the user. Profile data representative of the user profile is then used to control or instantiate bots of the users, or of categories of users, according to the learned playstyle patterns.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 16, 2021
    Assignee: NVIDIA Corporation
    Inventors: Andrew Fear, Brian Burke, Pillulta Venkata Naga Hanumath Prasad, Abhishek Lalwani
  • Patent number: 10943387
    Abstract: This disclosure presents a technique for utilizing ray tracing to produce a high quality visual scene that includes shadows while minimizing computing costs. Since the scene quality and computing cost is directly proportional to the number of rays used, this technique can lower the number of rays needed for shadow region rendering while maintaining a targeted visual quality for the scene. The process includes generating a complex pixel mask based on depth boundary testing, and generating a penumbra mask based on the shadow regions. These masks can use distance/depth data to cull certain pixels from their respective analysis to reduce processing time. A penumbra area can then be denoised using the two masks and the distance/depth data. Finally, the depth boundary pixel computations, i.e., complex pixels, can be resolved. From these processes, a final shadow mask can be generated and sent to the rendering process to complete the scene rendering.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: March 9, 2021
    Assignee: Nvidia Corporation
    Inventor: Jon Story
  • Patent number: 10943882
    Abstract: An IC package including an integrated circuit die having a major surface and one or more solder bumps located on the major surface in at least one corner region of the major surface and a substrate having a surface, the surface including bump pads thereon. The major surface of the integrated circuit die faces the substrate surface, the one or more solder bumps are bonded to individual ones of the bump pads to thereby form a bond joint, the major surface of the integrated circuit die has a footprint area of at least about 400 mm2. A ratio of a coefficient of thermal expansion of the substrate (CTEsub) to a coefficient of thermal expansion of the integrated circuit die (CTEdie) is at least about 3:1. A method of manufacturing an IC package is also disclosed.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 9, 2021
    Assignee: Nvidia Corporation
    Inventors: Jayprakash Chipalkatti, Zuhair Bokharey, Don Templeton, Brian Schieck, Julie Lam, Prashant Pathak
  • Patent number: 10935788
    Abstract: A method for stereoscopically presenting visual content is disclosed. The method comprises identifying and distinguishing between a first type of content and a second type of content of a frame to be stereoscopically displayed. The method also comprises rendering the first type of content in a first left and a first right frame from a single perspective using a first stereoscopic rendering method. Further, the method comprises rendering the second type of content in a second left and a second right frame using a second, different stereoscopic method from two different perspectives. Additionally, the method comprises merging the first and second left frames and the first and second right frames to produce a resultant left frame and a resultant right frame. Finally, the method comprises displaying the resultant left frame and the resultant right frame for stereoscopic perception by a viewer.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: March 2, 2021
    Assignee: NVIDIA Corporation
    Inventors: Patrick Neill, Rochelle Pereira, Vukasin Milovanovic, David Cook
  • Patent number: 10931266
    Abstract: A flip-flop element is configured to gate the clock inversions within a master-slave flip-flop element. The flip-flop element reduces the number of circuit elements within the flip-flop element by collapsing elements with common functionality into a single circuit element. Further, by making the actions of judiciously selected circuit elements conditional upon the state of the input data, the flip-flop element circuit reduces the number of internal transitions. In this manner, by reducing the number of circuit elements as well as the number of transitions, the flip-flop element achieves substantial reduction in overall system power consumption, resulting in a more efficient system.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: February 23, 2021
    Assignee: NVIDIA Corporation
    Inventors: Ilyas Elkin, Ge Yang, Xi Zhang, Jiani Yu
  • Patent number: 10929654
    Abstract: Estimating a three-dimensional (3D) pose of an object, such as a hand or body (human, animal, robot, etc.), from a 2D image is necessary for human-computer interaction. A hand pose can be represented by a set of points in 3D space, called keypoints. Two coordinates (x,y) represent spatial displacement and a third coordinate represents a depth of every point with respect to the camera. A monocular camera is used to capture an image of the 3D pose, but does not capture depth information. A neural network architecture is configured to generate a depth value for each keypoint in the captured image, even when portions of the pose are occluded, or the orientation of the object is ambiguous. Generation of the depth values enables estimation of the 3D pose of the object.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: February 23, 2021
    Assignee: NVIDIA Corporation
    Inventors: Umar Iqbal, Pavlo Molchanov, Thomas Michael Breuel, Jan Kautz
  • Patent number: 10929987
    Abstract: A neural network model receives color data for a sequence of images corresponding to a dynamic scene in three-dimensional (3D) space. Motion of objects in the image sequence results from a combination of a dynamic camera orientation and motion or a change in the shape of an object in the 3D space. The neural network model generates two components that are used to produce a 3D motion field representing the dynamic (non-rigid) part of the scene. The two components are information identifying dynamic and static portions of each image and the camera orientation. The dynamic portions of each image contain motion in the 3D space that is independent of the camera orientation. In other words, the motion in the 3D space (estimated 3D scene flow data) is separated from the motion of the camera.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: February 23, 2021
    Assignee: NVIDIA Corporation
    Inventors: Zhaoyang Lv, Kihwan Kim, Deqing Sun, Alejandro Jose Troccoli, Jan Kautz