Abstract: A CAN module that can be integrated between a CAN controller and a CAN transceiver includes a receive data (RXD), input interface for receiving a first bit sequence through a RXD stream and a RXD output interface for sending a manipulated receive data (MRXD), stream including a second bit sequence. A processing logic of the CAN module is configured to manipulate the first bit sequence to generate a second bit sequence comprising a second stuff bit at a second position in the second bit sequence corresponding to a first position of a first stuff bit in the first bit sequence such that the second stuff bit is complementary to a preceding bit of the second stuff bit in the second bit sequence. The present disclosure also relates to a method for the CAN module.

Abstract: Field effect transistors in an electronic switching device are provided with electrostatic discharge (ESD) protection elements electrically coupled to a first current terminal of each transistor (e.g., a source of each transistor or a drain of each transistor), allowing the electronic switching device to withstand ESD-induced currents without damage to the switching device.

Abstract: It is described a method, a control device, and a computer program for enabling/disabling at least one near field communication (NFC) function of a mobile device (MD). It is further described such a MD. The method comprises (a) associating the at least one NFC function to be enabled/disabled with a corresponding secure application (SA) installed in a secure element (SE) system; (b) checking whether the SA complies with a predefined secure condition; (c) if the SA complies with the predefined secure condition, transmitting a notification from the SA to the NFC control system (NFCC) via an interface between the SE system and the NFCC; and (d) enabling/disabling, by the NFCC, the at least one NFC function based on information comprised by the transmitted notification.

Abstract: A method is provided for partitioning a plurality of devices in a communications system. The method includes providing the communications system with a central server that communicates with each of the plurality of devices. The communications system communicates in a plurality of time periods. The plurality of devices is partitioned into two or more groups of devices. Time periods of the plurality of time periods are assigned for communications of the two or more groups of devices. Time intervals between the time periods for the two or more groups are determined to be co-prime time intervals greater than one, and each of the two or more groups is assigned a different time interval of the co-prime time intervals. The two or more groups are active for communications only during the assigned time periods determined by the co-prime time intervals. A device is also provided for operating in the communications system.

Abstract: Various implementations relate to a data processing system comprising instructions embodied in a non-transitory computer readable medium, the instructions for a cryptographic operation including a masked decomposition of a polynomial a having ns arithmetic shares into a high part a1 and a low part a0 for lattice-based cryptography in a processor, the instructions, including: performing a rounded Euclidian division of the polynomial a by a base ? to compute t(?)A; extracting Boolean shares a1(?)B from n low bits of t by performing an arithmetic share to Boolean share (A2B) conversion on t(?)A and performing an AND with ??1, where ?=???1 is a power of 2; unmasking a1 by combining Boolean shares of a1(?)B; calculating arithmetic shares a0(?)A of the low part a0; and performing a cryptographic function using a1 and a0(?)A.

Abstract: Various embodiments relate to a system for provisioning a cryptographic device, including: a memory; a processor coupled to the memory, wherein the processor is further configured to: determine a maximum PQC private key size, maximum PQC public key size, and maximum PQC updater size of a plurality of post quantum cryptography algorithms; provision memory in the cryptographic device to store a PQC-update non-PQC private key, a secret PQC-update non-PQC public key, PQC private key, PQC public key, and PQC updater based upon the determined maximum PQC private key size, maximum PQC public key size, and maximum updater size; and provision the cryptographic device with the PQC-update non-PQC private key, the secret PQC-update non-PQC public key, a non-PQC secret key, a non-PQC public key, and non-PQC algorithm code configured to carry out non-PQC cryptographic algorithms.

Abstract: A radar processor for processing a frame of radar data received from one or more targets, the frame of radar data having a carrier frequency and comprising a sequence of codewords with a codeword repetition interval, wherein the carrier frequency and the codeword repetition interval define an unambiguous velocity range, the radar processor configured to: receive the frame of radar data; transform the frame to obtain a velocity data array; apply a correction algorithm to the velocity data array to correct a Doppler shift of the frame to obtain a corrected array, wherein the correction algorithm comprises a set of Doppler correction frequencies corresponding to a set of velocity gates and at least one of the set of Doppler correction frequencies corresponds to a velocity gate outside the unambiguous velocity range; and perform range processing on the corrected array to obtain a range-Doppler map.

Abstract: Electrostatic discharge protection circuitry includes a transistor pass-gate coupled between potential source of electrostatic discharge-driven current (“ESD current”) and an input node of a circuit block is configured provide a sufficiently resistive current path between a first current terminal and a second current terminal of the pass gate such that, when an amount of charge sufficient to cause an ESD event accumulates at the potential ESD current source, a sufficient voltage drop occurs across the pass gate such that devices coupled to the input node of the circuit block are protected from experiencing a voltage drop across them that is above a predetermined threshold voltage.

Abstract: A data processing system has a processor and a system memory. The system memory may be a dynamic random-access memory (DRAM). The processor includes an embedded memory. The system memory is coupled to the processor and is organized in a plurality of pages. A portion of the code or data stored in the plurality of memory pages is selected for permutation. A permutation order is generated and the memory pages containing the portion of code or data is permuted using a permutation order. The permutation order and/or a reverse permutation order to recover the original order may be stored in the embedded memory. Permuting the memory pages with a permutation order stored in the embedded memory prevents the code or data from being read during a freeze attack on the system memory in a way that is useful to an attacker.

Abstract: A delta-sigma modulator including force circuitry that receives an output digital signal and provides a forced digital signal with a predetermined force state based on a force control signal, a combiner that subtracts the forced digital signal from the output digital signal for providing a digital error signal, and force correction circuitry that converts the digital error signal into one or more analog error correction signals applied to corresponding inputs of loop filter circuitry. The digital error signal and the force control signal may each be used to develop corresponding analog feedback signals used to adjust an analog input signal. The digital error signal may also be converted to one or more correction signals applied to corresponding inputs of the loop filter circuitry to correct the output digital signal. The digital error signal may also be used by a digital noise cancellation filter to further correct the output digital signal.

Abstract: A method is provided for watermarking a machine learning model used for object detection. In the method, a first subset of a labeled set of ML training samples is selected. Each of one or more objects in the first subset includes a class label. A pixel pattern is selected to use as a watermark in the first subset of images. The pixel pattern is made partially transparent. A target class label is selected. One or more objects of the first subset of images are relabeled with the target class label. In another embodiment, the class labels are removed from objects in the subset of images instead of relabeling them. Each of the first subset of images is overlaid with the partially transparent and scaled pixel pattern. The ML model is trained with the set of training images and the first subset of images to produce a trained and watermarked ML model.

Abstract: A circuit that includes a level shifter. The level shifter includes a shift path with two transistors coupled in series. The circuit also includes a GIDL detection circuit for detecting GIDL current conditions. The GIDL detection circuit generates a GIDL signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a transistor of the shift path to increase the conductivity of the transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least a portion of the shift path when the second transistor is nonconductive due to the level shifter being in a low power mode.

Abstract: A sensor node is provided having a radio frequency (RF) circuit and a sensor interface circuit. The RF circuit wirelessly harvests energy from an external device such as a smart phone to produce a voltage at an output to charge a storage capacitor. The sensor interface circuit is configured to communicate with a sensor. In response to a request from the external device, the sensor node provides a voltage level of the capacitive element to the external device. The external device uses the voltage level to determine capabilities of the sensor node and to control sensing functions of the sensor node. In another embodiment, a method is provided to operate the sensor node.

Abstract: A method and apparatus are provided in which receiver circuitry and signal processing circuitry may reside. The receiver circuitry receives a FMCW radar signal having a content signal (e.g., a random or information signal) embedded into a radar waveform and indicating a relationship in the FMCW radar signal between beat frequency and time delay. The signal processing circuitry may apply a filter (e.g., filtering with a group delay that approximates or relates to the relationship) that causes a residual error in, due to dispersion of, the content signal, and may account for (e.g., mitigate) the residual error by introduction of a dispersion-related function in further processing of the content signal.

Abstract: A semiconductor device and fabrication method are described for integrating stacked top and bottom nanosheet transistors by providing a nanosheet transistor stack having bottom and top Si/SiGe superlattice structures (11-14, 17-20) which are separated from one another by a barrier oxide layer (15) and which are separately processed to form first remnant silicon germanium nanosheet layers (12, 14) in the bottom Si/SiGe superlattice structures having a first gate length dimension (DG1) and to form second remnant silicon germanium nanosheet layers (18, 20) in the top Si/SiGe superlattice structures having a second, smaller gate length dimension (DG2) so that the nanosheet transistor stack may then be processed to simultaneously form bottom and top gate electrodes which replace, respectively, the first and second remnant silicon germanium nanosheet layers.

Abstract: A power combiner/splitter for multiple input multiple output (MIMO) applications and a method of making the same. A metallisation stack has a plurality of layers including patterned metal features forming first and second branched arrangements of the power combiner/splitter. Each branched arrangement includes a port located at one end of that branched arrangement, and a plurality of further ports. Each branched arrangement also includes a plurality of bifurcated branches extending between each end of that branched arrangement for dividing/combining a signal passing through that branched arrangement between the port and the plurality of further ports. The metallisation stack further includes a common ground plane that is shared by the first and second branched arrangements. At least some of the patterned metal features forming the first branched arrangement overlie at least some of the patterned metal features forming the second branched arrangement.

Abstract: A compact planar balun formed on a substrate including a hairpin-shaped conductive microstrip and a single-ended contact. The hairpin-shaped conductive microstrip includes first and second linear segments integrally formed with a U-shaped segment, and a single-ended contact is conductively coupled at a location along the first linear segment. The first and second linear segments each have a first characteristic impedance and are in parallel with each other having a first end forming first and second differential contacts and having a second end. The U-shaped segment has a second characteristic impedance that is less than the first characteristic impedance in order to achieve proper scatter parameter alignment. The U-shaped segment may be generally formed thicker or wider than the linear segments to achieve a reduced characteristic impedance. In the alternative or in addition, co-planer ground metal is formed closer to the U-shaped segment to achieve a reduced characteristic impedance.

Abstract: A signal processor and method of signal processing for a radio receiver is described. An input signal is received together with a spectral repetition interval value of an interferer signal. An interference reference signal is generated from the received spectral repetition interval value and the received signal. The received signal is adapted using the generated interference reference signal.

Abstract: An infrastructure-controller (206) for an infrastructure (202), wherein the infrastructure has a plurality of Bluetooth Low Energy, “BLE”, nodes (208, 210, 212) associated with it. The infrastructure-controller (206) is configured to: identify one of the plurality of BLE nodes as a current-BLE-node (212), and activate the current-BLE-node (212) for communication with a key (204) using BLE signals; determine a communication-quality-indicator for each of the plurality of BLE nodes (208, 210, 212), that represents the quality of communication with the key (204); based on the communication-quality-indicators, identify one of the plurality of BLE nodes as a next-BLE-node (210); and provide connection-information to the next-BLE-node (210) using out-of-band signalling (214). The infrastructure-controller (206) can then deactivate the current-BLE-node (212); and activate the next-BLE-node (212) for continued communication with the key (204) using BLE signals.

Abstract: A radar system, apparatus, architecture, and method are provided with a transmitter that produces a plurality of distinct FanTOM signals that are transmitted as N RF-encoded transmit signals in an overlapped fashion such that the pulse repetition interval and frame length are kept short; a receiver that processes target return signals reflected from the N RF-encoded transmit signals with a mixer to produce an IF signal which is filtered with one or more notch filters clocked with a sampling clock frequency to control harmonic notch frequencies to suppress transmitter spill-over and close-in self-clutter interference, thereby producing a filtered IF signal that is converted to a digital signal with an analog-to-digital converter that is clocked with the sampling clock frequency; and a radar processor that processes the digital signal to generate a range spectrum comprising N segments that correspond, respectively, to the N RF-encoded transmit signals.