Patents Assigned to NXP B.V.
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Patent number: 12154643Abstract: In a non-volatile memory (NVM) system of a memory device, a memory controller connected to memory cell arrays of the NVM system is configured to perform the steps of selecting a memory cell to test, energizing a test circuit connected to the memory cell under a first biasing condition, reading a measurement of an electrical property of the memory cell, and determining, based on the measurement, whether the memory cell is formed or unformed. In embodiments, the system and method include protecting the test circuit from attack by validating the results of the testing. The memory controller is further configured to energize the test circuit under a second biasing condition that produces a known test result whether the memory cell is formed or unformed; if the result of the second test is not the expected result, the memory controller determines that the testing circuit is malfunctioning or under attack.Type: GrantFiled: December 20, 2022Date of Patent: November 26, 2024Assignee: NXP B.V.Inventor: Soenke Ostertun
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Patent number: 12148820Abstract: Placement of a field plate in a field-effect transistor is optimized by using multiple dielectric layers such that a first end of field plate is separated from a channel region of the transistor by a first set of one or more distinct dielectric material layers. A second end of the field plate overlies the channel region and a control electrode from which it is separated by the first set of dielectric layers and one or more additional dielectric layers.Type: GrantFiled: December 20, 2021Date of Patent: November 19, 2024Assignee: NXP B.V.Inventors: Congyong Zhu, Bernhard Grote, Bruce McRae Green
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Patent number: 12141636Abstract: There is described an RFID tag IC, comprising: i) an NFC interface configured to initiate a power-up, when coupled with an HF field, and receive a read command from an RFID device; ii) a non-volatile memory, wherein the non-volatile memory is configured to store a counter value; and iii) a processing unit configured to increment the counter value when coupled with the HF field, set an increment flag, when the increment is successful, and thereby block a further increment of the counter value, in particular when fulfilling the read command, and reset the increment flag after fulfilling the read command. Further, a communication system and a method of operating are described.Type: GrantFiled: March 16, 2022Date of Patent: November 12, 2024Assignee: NXP B.V.Inventors: Christian Schwar, Christian Weidinger, Franz Amtmann, Heinz Umfahrer, Christoph Hans Joachim Garbe, Thomas Pichler
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Patent number: 12142527Abstract: Speed of plasma etching is regulated in regions prone to over-etching by providing an etch resistant structure, such as a metal saw bow, in the region. By adjusting dimensions, such as the length and width of the saw bow legs and an area defined by the saw bow legs, as well as a shape of the etch region through techniques such as chamfering, plasma etch speed in the region can be controlled with an intent to match the speed of etching in non-over-etched regions.Type: GrantFiled: June 14, 2023Date of Patent: November 12, 2024Assignee: NXP B.V.Inventors: Antonius Hendrikus Jozef Kamphuis, Ernst Eiper, Johannes Cobussen, Chantal Claude Dijkstra
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Patent number: 12137339Abstract: Disclosed is a UWB communication node comprising: a UWB communication unit configured to transmit one or more messages, to a plurality of external responder nodes and comprising a ranging control message defining a contention period, and further configured to receive one or more responses from said responder nodes during said contention period, each response including a response payload; a processor unit configured to use a common cryptographic session key to encrypt said messages; wherein the processing unit is further configured to use responder-specific session keys to decrypt the response payloads; wherein each individual one of said responder-specific cryptographic session keys is a unique key shared between the node and one of the external responder nodes. Corresponding systems methods and an associated computer program are also disclosed.Type: GrantFiled: January 28, 2022Date of Patent: November 5, 2024Assignee: NXP B.V.Inventors: Srivathsa Masthi Parthasarathi, Stefan Lemsitzer
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Patent number: 12137010Abstract: A battery pack comprises an enclosure; a plurality of network nodes that communicate with each other inside the enclosure and that generate a unique radio frequency (RF) signature; and a special-purpose computer processor that compares an incoming channel impulse response (CIR) of the unique radio frequency (RF) signature corresponding to an incoming packet to a plurality of stored valid RF CIR signatures and executes a resemblance metric to accept or reject the incoming packet.Type: GrantFiled: May 3, 2022Date of Patent: November 5, 2024Assignee: NXP B.V.Inventors: Klaas Brink, Vincent Pierre Martinez, Cornelis Marinus Moerman
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Patent number: 12135358Abstract: An apparatus and method for measuring energy cell impedance. Time sequences representing each of a repetitive signal, an orthogonal-phase-repetitive signal at the characterizing frequency, and at least one term of a power series polynomial are generated. One of a current or voltage corresponding to the repetitive signal is applied to an energy cell. Contemporaneously with the applying, measured values of a current or voltage are measured. A set of correlation values between the measured values and the generated time sequences are determined. The set of correlation values are transformed into a set of fitted coefficients of a repetitive signal component and an orthogonal-phase-repetitive signal component at a characterizing frequency. An impedance of the energy cell at the characterizing frequency is determined based on a ratio of the fitted coefficients for the orthogonal-phase-repetitive component to the repetitive signal component.Type: GrantFiled: December 15, 2022Date of Patent: November 5, 2024Assignee: NXP B.V.Inventors: Matheus Johannus Gerardus Lammers, Henri Verhoeven, Oswald Moonen, Edwin Schapendonk
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Patent number: 12132816Abstract: There is provided, a method for clock recovery in a RFID tag, the method includes receiving a RF field from a RFID reader. A field clock is generated from the received RF field, from which a clock recovery signal is generated. The RF field is modulated to produce a RF modulation. Generation of the clock recovery signal is paused while the RF field is being modulated. A modulation envelope signal is generated and used for load modulation. Generation of the clock recovery signal at the end of the RF modulation is resumed after a delay of one clock cycle from a falling edge of the modulation envelope signal. In another embodiment of the method, instead of adding the delay, a differential amplifier is used to increase RF field detection sensitivity. The method and the RFID tag ensures synchronized resumption of a PLL clock and the clock recovery signal.Type: GrantFiled: January 4, 2023Date of Patent: October 29, 2024Assignee: NXP B.V.Inventors: Rainer Stadlmair, Shankar Joshi, Raghavendra Kongari
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Patent number: 12130373Abstract: A method, a system, and a device for wireless localization are disclosed. In an embodiment, the method includes performing, by a localization device, Two-Way Ranging (TWR) and Time Difference of Arrival (TDOA) in parallel, where the TWR is performed with a receiving device to determine a distance between the localization device and the receiving device, and the TDOA is performed with anchors to determine a geolocation of the localization device, and determining, using the distance and the geolocation, a position of the localization device relative to the receiving device.Type: GrantFiled: April 25, 2022Date of Patent: October 29, 2024Assignee: NXP B.V.Inventors: Ghiath Al-kadi, Stefan Lemsitzer
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Patent number: 12125771Abstract: A semiconductor package comprises a leadframe, a component module, and a semiconductor die. The leadframe has a plurality of insertion terminals, a split die pad, and one or more leads. The component module has one or more passive components mounted on a substrate. The semiconductor die has an integrated circuit. The component module is mounted on a split die pad at a first surface of the leadframe and forms an electrical connection with the insertion terminals. Further, the semiconductor die is mounted on the split die pad at a second surface of the leadframe which is opposite to the first surface.Type: GrantFiled: December 8, 2021Date of Patent: October 22, 2024Assignee: NXP B.V.Inventors: Chayathorn Saklang, Chanon Suwankasab, Amornthep Saiyajitara, Verapath Vareesantichai
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Patent number: 12126351Abstract: Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal. Hereby, the digital inputs provided to the DACs are non-randomized.Type: GrantFiled: December 5, 2022Date of Patent: October 22, 2024Assignee: NXP B.V.Inventors: Robert Rutten, Muhammed Bolatkale, Lucien Johannes Breems
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Patent number: 12126366Abstract: Embodiments of multi-mode sigma-delta analog-to-digital converter (ADC) circuits and a microphone circuit are disclosed. In an embodiment, a multi-mode sigma-delta ADC circuit includes a pair of operational transconductance amplifiers (OTAs), a filter connected to the pair of OTAs, a quantizer connected to the filter, a differential digital-to-analog converter (DAC) connected to the quantizer, and a controller configured to switch the multi-mode sigma-delta ADC circuit between a single-ended operational mode, a pseudo differential operational mode, and a full differential operational mode to improve common mode rejection (CMR) performance by controlling the pair of OTAs. An output of a microphone and a differential output of the differential DAC are inputted into input terminals of the pair of OTAs.Type: GrantFiled: September 22, 2022Date of Patent: October 22, 2024Assignee: NXP B.V.Inventors: Dave Sebastiaan Kroekenstoel, Muhammad Kamran, Harry Neuteboom, Costantino Ligouras, Sergio Andrés Rueda Gómez
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Patent number: 12126248Abstract: There is described a method of controlling a single inductor multiple output, SIMO, switching converter, the method comprising (a) counting, for each output of the multiple outputs of the SIMO switching converter, a period of time during which an output voltage at the respective output is below a corresponding individual threshold value, (b) identifying that output among the multiple outputs of the SIMO switching converter for which the counted period of time is longest, and (c) connecting the identified output to the single inductor of the SIMO switching converter to supply current from the single inductor of the SIMO switching converter to the identified output. Furthermore, a corresponding controller is described.Type: GrantFiled: February 18, 2022Date of Patent: October 22, 2024Assignee: NXP B.V.Inventors: Christian Vincent Sorace, Nicolas Patrick Vantalon, Ludovic Oddoart, Fabien Boitard
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Patent number: 12124347Abstract: An integrated circuit (IC) includes first and second secure memory elements storing identical data and a memory management system that executes a memory operation on the first secure memory element and a control operation on the second secure memory element simultaneously. The control operation is associated with safety of the IC and is executed to enable error detection in the second secure memory element, fault injection for the second secure memory element, masking of a power profile associated with the memory operation, or a combination thereof. After the execution of the memory operation and the control operation, the memory management system copies the data of the first secure memory element to the second secure memory element to maintain sanity of the second secure memory element.Type: GrantFiled: January 11, 2023Date of Patent: October 22, 2024Assignee: NXP B.V.Inventors: Neha Srivastava, Gautam Tikoo, Harshit Saxena
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Patent number: 12127091Abstract: A wearable safety apparatus including a body area network (BAN) transceiver for communicating with a user-controlled apparatus is described. The BAN transceiver includes a processor coupled to a BAN antenna. The processor is configured to receive an identification data request from a user-controlled apparatus in response to an action request of a user of the wearable safety apparatus; and to transmit identification data to the user-controlled apparatus in response to the identification data request. The identification data validates the user action by the user-controlled apparatus. The identification data request is only received when the wearable safety apparatus and the user-controlled apparatus are in contact with the user.Type: GrantFiled: October 5, 2021Date of Patent: October 22, 2024Assignee: NXP B.V.Inventors: Pramod Rajan Kesavelu Shekar, Rinze Ida Mechtildis Peter Meijer, Anand Shirwal
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Patent number: 12125780Abstract: A method of manufacturing a semiconductor device is provided. The method includes attaching a first end of a first bond wire to a first conductive lead and a second end of the first bond wire to a first bond pad of a first semiconductor die. A conductive lead extender is affixed to the first conductive lead by way of a conductive adhesive, the lead extender overlapping the first end of the first bond wire. A first end of a second bond wire is attached to the lead extender, the first end of the second bond wire conductively connected to the first end of the first bond wire.Type: GrantFiled: December 4, 2023Date of Patent: October 22, 2024Assignee: NXP B.V.Inventor: Mei Yeut Lim
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Patent number: 12123970Abstract: Aspects of the present disclosure are directed to radar and radar processing. As may be implemented in accordance with one or more embodiments involving multi-input multi-output (MIMO) co-prime radar signals transmitted by a plurality of transmitters and reflected from at least one target, the reflected radar signals are processed by resolving ambiguities associated with a range-Doppler detection based on unique pulse repetition frequencies (PRF)s associated with respective chirp groups of the reflected radar signals. Phase compensation is applied to compensate for motion-induced phased biases and, thereafter, Doppler estimates are reconstructed to provide a dealiased version of the reflected radar signals.Type: GrantFiled: September 24, 2021Date of Patent: October 22, 2024Assignee: NXP B.V.Inventors: Ryan Haoyun Wu, Dongyin Ren, Satish Ravindran
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Patent number: 12123966Abstract: Described are method and systems that implement time frequency domain threshold interference and localization fusion to resolve interference issues in an automotive radar system, that produces spectrograms using Short-Time Fourier Transform (STFT) for all receiving antennas of the automotive radar system. For each STFT frequency a suppression threshold is determined. Interference is isolated for each STFT frequency by removing the interference from samples that are above the suppression threshold by using a filter. Direction of Arrival (DoA) is estimated for each interference spectrogram cell using measurements from all the receiving antennas. Interference samples are clustered using the DoA into epochs of chirps.Type: GrantFiled: November 23, 2021Date of Patent: October 22, 2024Assignee: NXP B.V.Inventors: Ryan Haoyun Wu, Feike Guus Jansen, Michael Andreas Staudenmaier, Maik Brett
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Patent number: 12126365Abstract: A continuous-time delta-sigma modulator, CTDSM (400, 500, 700, 800) is described that comprises: an operational transconductance amplifier, OTA, (406, 506, 706, 806) having an input port (404, 504, 719, 739, 819, 839) configured to receive an analog input signal and an output port (408, 508, 707, 708, 807, 808); an input low pass filter network comprising at least one input resistor, R1, (402, 502, 702, 722, 802, 822) at least one first shunt capacitor, C1, (403, 503, 703, 803) and at least one feedback resistor, Rdac (410, 510, 710, 810, 730, 830) connected to the input port of the OTA; an output filter network comprising a shunt second resistor, R2, (415, 515, 715, 815) in parallel to a second shunt capacitor, C2, (414, 514, 714, 814), and coupled to the output port (408, 508, 707, 708, 807, 808) of the OTA; a quantizer (413, 513, 713, 813) connected to the output filter network and having at least one output connected to the input port of the OTA via the at least one feedback resistor, Rdac; and wherein thType: GrantFiled: November 3, 2022Date of Patent: October 22, 2024Assignee: NXP B.V.Inventors: Victor Pecanins Martinez, Robert van Veldhoven
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Patent number: 12124385Abstract: Aspects of the disclosure are directed to allocating bandwidth. As may be implemented in accordance with one or more embodiments, respective amounts of bandwidth are allocated to respective application groups for each memory access cycle in a set of memory access cycles. Initial bonus bandwidth is provided to a first one of the application groups during one of the memory access cycles. The bonus bandwidth may include at least a portion of bandwidth allocated to and unused by one of the other respective application groups during the memory access cycle. Additional bonus bandwidth is selectively provided to the first application group during one of the memory access cycles based on the initial bonus bandwidth and a maximum amount of bonus bandwidth defined for the set of memory access cycles, in response to bandwidth allocated to one of the other respective application groups during the subsequent memory access cycle being unused.Type: GrantFiled: October 28, 2022Date of Patent: October 22, 2024Assignee: NXP B.V.Inventors: James Andrew Welker, Vaibhav Kumar, Rohit Kumar Kaul, Ankush Sethi