Patents Assigned to NXP B.V.
  • Patent number: 12074124
    Abstract: An integrated circuit package comprising an encapsulant, a semiconductor die in the encapsulant the semiconductor die comprising a plurality of die terminals, an integrated waveguide launcher, wherein the integrated waveguide launcher is connected to one of the die terminals and a land grid array provided on a bottom surface of the package. The land grid array comprises a plurality of package terminals, each package terminal configured to be soldered to a printed circuit board, and an opening, wherein the opening is aligned with the integrated waveguide launcher.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: August 27, 2024
    Assignee: NXP B.V.
    Inventors: Abdellatif Zanati, Adrianus Buijsman, Dominik Xaver Simon
  • Patent number: 12066520
    Abstract: Aspects of the present disclosure are directed to radar communications with disparate pulse repetition intervals, as may be implemented with radar transmission, receiver and processing circuitry. As may be utilized in accordance with one or more embodiments herein, time division multiplexing (TDM) multi-input multi-output (MIMO) radar signals are transmitted by transmitting sets of successive radar signals, each set having a pulse repetition interval (PRI) that is different than the PRI of sets of radar signals transmitted in another one of the sets. Positional characteristics of a target may be ascertained based on the PRI used in each of the sets and on phase characteristics of ones of the radar signals reflected from the target.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: August 20, 2024
    Assignee: NXP B.V.
    Inventors: Ryan Haoyun Wu, Dongyin Ren, Wendi Zhang, René Geraets
  • Patent number: 12063045
    Abstract: The disclosure relates to monitoring of feedback systems such as phase lock loops. A system is disclosed, comprising: a feedback circuit (100); and a monitoring module (190). The monitoring module (190) is configured to: i) receive actual values of at least one state variable describing the state of the feedback circuit at a first time; ii) determine a predicted future value of the at least one state variable at a second time from the actual values at the first time using a model of the feedback circuit; iii) receive actual values of the at least one state variable at the second time; iv) compare the predicted future value of the at least one state variable at the second time with the actual value of the at least one state variable at the second time; and v) determine whether the feedback circuit has a fault condition, depending on the results of step iv).
    Type: Grant
    Filed: October 20, 2021
    Date of Patent: August 13, 2024
    Assignee: NXP B.V.
    Inventors: Ulrich Moehlmann, Jan-Peter Schat, Tim Lauber
  • Patent number: 12062982
    Abstract: A boost converter comprises a comparator circuit including: a first input port configured to receive an off-time sawtooth voltage a second input port configured to receive an on-time sawtooth voltage, the comparator circuit comparing the off-time sawtooth voltage and on-time sawtooth voltage to generate trigger signal including a differential ripple voltage that is output by an output port to a power stage circuit. The boost converter further comprises a reference voltage source that provides a reference voltage to the first input port and a feedback circuit that provides the on-time sawtooth voltage to the second port, wherein the differential ripple voltage emulates an inductor current or voltage of an output capacitor of the power stage circuit.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: August 13, 2024
    Assignee: NXP B.V.
    Inventor: Henricus Cornelis Johannes Buthker
  • Patent number: 12061228
    Abstract: A device comprises a substrate and a stacked bond ball structure. The substrate comprises a bond pad, and the stacked bond ball structure comprises a first and a second bond ball. The first bond ball is in contact with the bond pad, and the second bond ball is positioned on the first bond ball. The stacked bond ball structure is configured to be coupled to a resistance-sensing circuit, such that a resistance of an interface between the first bond ball and the bond pad can be measured to determine an amount of degradation of the interface between the first bond ball and the bond pad. In some implementations, the device further comprises a controller configured to obtain a measured resistance of the interface from the resistance-sensing circuit and determine the amount of degradation of the interface based at least in part on the measured resistance.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: August 13, 2024
    Assignee: NXP B.V.
    Inventors: Michiel van Soestbergen, Amar Ashok Mavinkurve
  • Patent number: 12052051
    Abstract: An ultra-wideband, UWB, receiver module (213) comprising: an antenna for wirelessly receiving UWB signalling from a UWB transmitter module (212) and a processor. The processor is configured to: determine a channel impulse response, CIR, (519) of the wirelessly received UWB signalling, wherein the CIR comprises a plurality of channel taps each having a tap-response-value; identify a predetermined feature (520) in the CIR and an associated channel tap; and based on the channel tap that is associated with the identified feature (520) in the CIR (519), synchronize the UWB receiver module (213) for reception of subsequent UWB signalling.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: July 30, 2024
    Assignee: NXP B.V.
    Inventors: Stefan Tertinek, Wolfgang Küchler, Sandeep Mallya, Pradeep Kumar Aithagani
  • Patent number: 12050512
    Abstract: A method of dynamic configuration of reaction policies in virtualized fault management system includes disabling a fault handler circuit comprising a reaction core in response to receiving a request to modify a respective first reaction policy including a plurality of first recovery actions of the reaction core, wherein each of the first recovery actions is responsive to a respective fault indication. At least one event status is cleared from an event table of the fault handler circuit. The at least one event status is set in response to the fault handler circuit receiving the respective fault indication. The reaction core is configured with a second reaction policy including a plurality of second recovery actions.
    Type: Grant
    Filed: August 2, 2022
    Date of Patent: July 30, 2024
    Assignee: NXP B.V.
    Inventors: Shreya Singh, Sandeep Kumar Arya, Hemant Nautiyal
  • Patent number: 12050284
    Abstract: A vehicle radar system, apparatus and method use a radar control processing unit to generate a target response signal in at least a first dimension from compressed radar data signals and to perform cell-averaging constant false alarm rate (CA-CFAR) target detection by convolving the target response signal with a weighted kernel window signal in a frequency domain using a Fast Fourier Transform hardware accelerator, an element-wise multiplier, and an Inverse Fast Fourier Transform hardware accelerator to generate an output signal having a sign that indicates a target detection decision.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: July 30, 2024
    Assignee: NXP B.V.
    Inventors: Ryan Haoyun Wu, Satish Ravindran, Maik Brett
  • Patent number: 12051475
    Abstract: A system for verifying memory-read capabilities includes a memory device, having a memory cell array that is encoded with verification information, and a memory-read controller, coupled to the memory device and configured to execute stored process steps. The verification information includes first bit values encoded in a first row of the memory cell array and second bit values encoded in a second row of the memory cell array. Each of the second bit values on a same bit line as a corresponding one of the first bit values has an inverse value as the corresponding one of the first bit values. The stored process steps include steps to: read the verification information from the memory device; determine, by comparison to a pre-stored bit string, whether the first bit values and the second bit values are correct; and in response to an affirmative determination, initiate normal data-read operations.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: July 30, 2024
    Assignee: NXP B.V.
    Inventor: Hyungjoong Lee
  • Patent number: 12047491
    Abstract: Various embodiments relate to a hardware device configured to compute a plurality of chained hash functions in parallel, including: a processor implementing p hash functions configured to operate on a small input, where p is an integer; a data unit connected to the plurality of hash functions, configured to store the outputs of plurality of hash functions that are then used as the input to a next round of computing the hash function, wherein the processor receives a single instruction and p small data inputs, and wherein each of the p hash functions are used to perform a chained hash function operation on a respective small input of the p small inputs.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: July 23, 2024
    Assignee: NXP B.V.
    Inventors: Joppe Willem Bos, Mario Lamberger, Joost Roland Renes, Tobias Schneider, Christine van Vredendaal
  • Patent number: 12047489
    Abstract: An apparatus configured to: receive a digital input signal; receive a processing-direction-signal that can have a forward-value or a backward-value; and provide a digital output signal. The apparatus comprising a processor configured to apply an involutional cryptographic function to the digital input signal by: for a first operation: apply a first step of the involutional cryptographic function to the digital input signal in order to implement a forward calculation to move to the next step in the sequence; and perform a plurality of further operations until the forward calculation of a last step is performed. Each further operation comprises: if the processing-direction-signal has a forward-value: then perform the forward calculation for the current step; or if the processing-direction-signal has a backward-value: then perform a backward calculation for the current step.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: July 23, 2024
    Assignee: NXP B.V.
    Inventors: Jan-Peter Schat, Andreas Lentz, Fabrice Poulard
  • Patent number: 12047113
    Abstract: In accordance with a first aspect of the present disclosure, a communication device is provided, comprising: at least two antennas; an ultra-wideband (UWB) communication unit configured to receive UWB frames through said antennas; a controller configured to switch between said antennas such that consecutive UWB frames are received through different ones of said antennas; wherein the controller is further configured to compute channel impulse responses (CIRs) wherein each of said CIRs is based on a different one of said UWB frames. In accordance with a second aspect of the present disclosure, a corresponding method of operating a communication device is conceived. In accordance with a third aspect of the present disclosure, a computer program is provided for carrying out said method.
    Type: Grant
    Filed: January 16, 2023
    Date of Patent: July 23, 2024
    Assignee: NXP B.V.
    Inventors: Stefan Tertinek, Manuel Lafer, Wolfgang Küchler
  • Patent number: 12040357
    Abstract: As disclosed herein, an integrated circuit substrate includes a first region coupled to a signal terminal and includes a guard region coupled via a diode circuit to a supply voltage terminal of the integrated circuit. The first region and the guard region are both of a first conductivity type. A cathode of the diode circuit is connected to the guard region and an anode of the diode circuit is connected to the supply voltage terminal. The first region and the guard region are separated by at least by a second region of the substrate that is of a second conductivity type opposite the first conductivity type.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: July 16, 2024
    Assignee: NXP B.V.
    Inventors: Guido Wouter Willem Quax, Dongyong Zhu
  • Patent number: 12041561
    Abstract: A wireless communication system (100) estimates a carrier frequency offset between wireless devices (101, 102) by configuring the devices through exchanging packet configuration packets (121, 125) to specify a carrier frequency offset fingerprint (CFOF) sequence in a measurement packet (133, 136) which is transmitted between the wireless devices, where the CFOF sequence in the measurement packet includes a prefix component (31), one or more signature segments (32), and a suffix component (33) for performing CFO measurements at the wireless devices which each process IQ samples corresponding to the signature segments in the received measurement packet by correlating the IQ samples against a reference vector to generate, for each of the one or more signature segments, a carrier frequency offset estimate between the first and second wireless devices.
    Type: Grant
    Filed: April 7, 2021
    Date of Patent: July 16, 2024
    Assignee: NXP B.V.
    Inventors: Raja Venkatesh Tamma, Khurram Waheed
  • Patent number: 12040034
    Abstract: Various embodiments relate to a method for storing and reading data from a memory. Data words stored in the memory may be grouped, and word specific parity information and shared parity information is generated, and the shared parity information is distributed among the group of words. During reading of a word, if more errors are detected than can be corrected with word parity data, the shared parity data is retrieved and used to make the error corrections.
    Type: Grant
    Filed: May 8, 2023
    Date of Patent: July 16, 2024
    Assignee: NXP B.V.
    Inventors: Soenke Ostertun, Björn Fay, Vitaly Ocheretny
  • Patent number: 12035133
    Abstract: A communication device and method are provided for communicating data, such as a cryptographic key, wirelessly to another communication device. The communication device and the other device each include an oscillator circuit portion, an inverter, a non-inverting buffer, and a switch for switching between the inverter and non-inverting buffer. A circular loop is formed wirelessly between the oscillator circuit portions of both devices by placing both communication devices near each other. A control circuit in each device measures a parameter such as frequency or waveform pattern of the circulating signal to determine how to position the switches. The oscillator circuit portions may be portions of the same oscillator distributed between the devices, such as a delay line-controlled oscillator or a chaotic oscillator. Inverting and not inverting the circulated signal changes the parameter of the signal so that it is difficult for an eavesdropper to learn the communication.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: July 9, 2024
    Assignee: NXP B.V.
    Inventor: Jan-Peter Schat
  • Patent number: 12032690
    Abstract: A method is provided for protecting a machine learning model from a side channel attack. A weighted sum vector having first and second elements is initialized. A weight vector for a connection between a node of a first layer and a node of a second layer is multiplied with an input vector to the node of the first layer. A first element of the weight vector includes a weight, and a first element of the input vector includes the input. A second element of the weight vector is a negation of the first element of the weight vector and the second element of the input vector equals the first element of the input vector. A multiplication result is added to the weighted sum vector to produce a computed weighted sum vector. An output vector including the computed weighted sum vector is provided to the node of the second layer.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: July 9, 2024
    Assignee: NXP B.V.
    Inventors: Jan Hoogerbrugge, Wilhelmus Petrus Adrianus Johannus Michiels
  • Patent number: 12034361
    Abstract: A controller for a DC-DC converter that includes an inductor. The DC-DC converter has three phases of operation: a first phase, in which an input voltage charges the inductor; a second phase, in which the inductor discharges to a load; and a third phase, in which the inductor is disconnected from the load and in which the input voltage does not charge the inductor. The controller is configured to set a control-factor based on the input voltage of the DC-DC converter, and set the duration of the third phase based on the control-factor and the sum of the duration of the first phase and the second phase.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: July 9, 2024
    Assignee: NXP B.V.
    Inventors: Wouter van der Heijden, Edwin Schapendonk, Henricus Cornelis Johannes Buthker, Henri Verhoeven, Oswald Moonen, Ton van Deursen
  • Patent number: 12032684
    Abstract: A method for detecting a fault injection is described. The method includes providing a secondary code, the secondary code including a predetermined function with a known expected result when the secondary code is executed with a known tested input. A primary code is executed in the data processing system. The primary code may be a portion of code that requires protection from a fault injection attack, such as for example, security sensitive code. The secondary code is executed in parallel with the primary code execution in the data processing system to produce an output. The output is compared with the known expected result to detect the fault injection attack of the data processing system. In one embodiment, the secondary code is not related to the primary code.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: July 9, 2024
    Assignee: NXP B.V.
    Inventors: Lars Kaufmann, Nikita Veshchikov
  • Patent number: 12034000
    Abstract: A double IO pad cell including a busing frame formed on a busing metal layer aligned with a same-sized component frame integrated on a component layer of an IC. The busing frame includes first and second IO pads, a supply voltage rail, and a ground voltage rail. The component frame includes first and second primary ESD circuitry each including a first diode coupled between a respective one of the first and second IO pads and the supply voltage rail and a second diode coupled between the respective IO pad and the ground voltage rail. The second diodes of each primary ESD circuitry are integrated adjacent each other sandwiched between the first diodes which act as collector guard bands for the second diodes. The diodes of each primary ESD circuitry of the component frame are aligned with a corresponding one of the first and second IO pads of the busing frame.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: July 9, 2024
    Assignee: NXP B.V.
    Inventors: Michael A. Stockinger, Mohamed Suleman Moosa