Patents Assigned to NXP B.V.
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Patent number: 12190936Abstract: A refresh circuit selects a candidate bank for refreshing from various banks of a dynamic random access memory (DRAM). Initially, the refresh circuit checks if any bank is idle (e.g., is not targeted for memory operations). If two or more banks are idle, the candidate bank is selected based on a count of accesses targeted to each occupied bank and bank-pair distances between each pair of idle and occupied banks. Conversely, if all banks are occupied, the refresh circuit selects the candidate bank based on a count of data accesses targeted to each bank and/or a count of parity accesses targeted to each bank. Each data access has the same type as that scheduled for execution on the DRAM. Once the candidate bank is selected, the refresh circuit triggers the refresh of the candidate bank.Type: GrantFiled: January 24, 2023Date of Patent: January 7, 2025Assignee: NXP B.V.Inventors: Suhas Chakravarty, James Andrew Welker
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Patent number: 12192949Abstract: There is disclosed devices and methods of operating a first device to determine a distance, between it and a further device, the methods comprising: transmitting a first broadcast frame comprising an identifier and a transmission timestamp; receiving a further broadcast frame, the further broadcast frame comprising an identifier of the further device, and a transmission timestamp of the further device, and at least one data pair comprising a transmitting device identifier and a reception timestamp, wherein the reception timestamp is indicative of the arrival time, at the further device, of a prior broadcast frame broadcast from the transmitting device; determining a reception timestamp of the further broadcast frame; comparing each transmitting device identifier with the identifier of the first device; and determining the distance between the first device and the further device.Type: GrantFiled: March 23, 2022Date of Patent: January 7, 2025Assignee: NXP B.V.Inventors: Sunil Dilipkumar Jogi, Giten Kulkarni
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Patent number: 12191688Abstract: In a battery management system, during a pre-charge mode, a first contactor is closed to provide a pre-charge current path from a low voltage battery supply node through a DCDC converter and through the first contactor to pre-charge a capacitor of an inverter for an electric motor. During a drive mode following the pre-charge mode, the first contactor is opened and a second contactor is closed to provide a drive mode current path from a high voltage battery supply node through the second contactor to the inverter to power the electric motor. In response to detecting an open fault in the second contactor during the drive mode, a limp mode is entered. During the limp mode, the first contactor is closed to provide a limp mode current path from the high voltage battery supply node through the first contactor to the inverter to power the electric motor.Type: GrantFiled: April 7, 2022Date of Patent: January 7, 2025Assignee: NXP B.V.Inventors: Antoine Fabien Dubois, Erik Santiago
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Patent number: 12191859Abstract: An integrated circuit including a functional circuit, a tuning circuit, and a control circuit is provided. The functional and control circuits generate an output signal and a digital code, respectively. The tuning circuit tunes the functional circuit based on the digital code to control an attribute of the output signal. The digital code is iteratively adjusted such that the attribute of the output signal is maintained within a predefined range. When the digital code corresponds to a cliff value, the digital code for a subsequent iteration is adjusted by a non-unit offset value such that a difference between the attribute for the cliff value and for the subsequent digital code is within a tolerance limit. The digital code is indicative of coarse and fine parameters, and for each value of the coarse parameter, the cliff value corresponds to the lowest or highest value of the fine parameter.Type: GrantFiled: June 9, 2023Date of Patent: January 7, 2025Assignee: NXP B.V.Inventors: Saurabh Goyal, Divya Tripathi, Krishna Thakur, Deependra Kumar Jain
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Patent number: 12184370Abstract: An antenna system for a mobile communications base station and a method of operating a communications network including a base station is described. The antenna system includes an antenna array for beamforming and is configured either as a radar sensor, a communications antenna or a combined radar sensor. A radar image may be used to determine a map of objects in the vicinity of the antenna system and to adapt the beamsteering or beamforming of the antenna system.Type: GrantFiled: May 12, 2023Date of Patent: December 31, 2024Assignee: NXP B.V.Inventors: Paul Mattheijssen, Konstantinos Doris, Dominicus Martinus Wilhelmus Leenaerts, Mark Tomesen
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Patent number: 12184308Abstract: An interface circuit includes an analogue to digital converter having an input configured to receive an input signal having an unknown DC bias voltage via an input resistance and provide an output signal to an ADC feedback loop. The ADC feedback loop includes a digital filter arranged to digitally filter the fedback output signal. A digital to analogue converter (DAC) forming a DC feedback loop with the ADC and arranged to convert the digitally filtered fedback output signal to an analogue signal that is provided to the input of the ADC, wherein the analogue signal that is provided to the input of the ADC is arranged to include a DC bias component that is comparable to a DC bias component of a current of the input signal passing through the input resistor.Type: GrantFiled: August 29, 2022Date of Patent: December 31, 2024Assignee: NXP B.V.Inventor: Robert van Veldhoven
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Patent number: 12183595Abstract: A method of forming an assembly is provided. The method includes attaching a packaged semiconductor device to a substrate. An isolation structure is formed and located between the packaged semiconductor device and the substrate. An underfill material is dispensed between the packaged semiconductor device and the substrate. The isolation structure prevents the underfill material from contacting a first conductive connection formed between the packaged semiconductor device and the substrate.Type: GrantFiled: December 12, 2022Date of Patent: December 31, 2024Assignee: NXP B.V.Inventors: Leo van Gemert, Peter Joseph Hubert Drummen
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Patent number: 12177338Abstract: Various embodiments relate to a system for provisioning a cryptographic device, including: a memory; a processor coupled to the memory, wherein the processor is further configured to: determine the maximum key generation seed size, maximum PQC private key size, maximum PQC public key size, and maximum PQC updater size of a plurality of post quantum cryptography algorithms; provision memory in the cryptographic device to store a key generation seed, PQC private key, PQC public key, and PQC updater based upon the determined maximum key generation seed size, maximum PQC private key size, maximum PQC public key size, and maximum PQC updater size; and provision the cryptographic device with a non-PQC secret key, a non-PQC public key, and non-PQC algorithm code configured to carry out non-PQC cryptographic algorithms.Type: GrantFiled: January 28, 2022Date of Patent: December 24, 2024Assignee: NXP B.V.Inventors: Christine Van Vredendaal, Mario Lamberger, Markus Hinkelmann, Hauke Meyn, Alexander Vogt
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Patent number: 12177153Abstract: Aspects of the present disclosure are directed to wireless communications involving successively-received messages. As may be implemented consistent with one or more aspects characterized herein, a preamble section (122) of a currently-received message (120) is used in decoding a previously-received message (110), for wireless transmissions from a wireless transmitter (102) on a wireless communications channel (101). The current and previous message are received in succession with a time gap (130) therebetween.Type: GrantFiled: March 1, 2021Date of Patent: December 24, 2024Assignee: NXP B.V.Inventors: Vincent Pierre Martinez, Alessio Filippi
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Patent number: 12174253Abstract: An electronic device includes a bias generator to generate a plurality of bias currents and a testing module to test the bias generator by successively testing each subset of bias currents of a plurality of subsets of bias currents grouped from the plurality of bias currents as a corresponding single test current. The testing module can include a variable resistor, wherein the testing module is to test the bias generator by, for each subset of bias currents, configuring the variable resistor to have a corresponding resistance based on the number of bias currents represented in the subset, conducting a corresponding test current through the variable resistor configured to the corresponding resistance, the test current representing a combination of all bias currents of the corresponding subset, and determining a test status for the subset of bias currents based on a voltage across the variable resistor resulting from the corresponding test current.Type: GrantFiled: March 21, 2023Date of Patent: December 24, 2024Assignee: NXP B.V.Inventors: Cristian Pavao Moreira, Thierry Mesnard, Michiel Alexander Hallie
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Patent number: 12177363Abstract: Various embodiments relate to a fault detection system and method for a digital signature algorithm, including: producing a digital signature of a message using a digital signature algorithm; storing parameters from a last round of the digital signature algorithm; executing the last round of the digital signature algorithm using the stored parameters to produce a check signature; comparing the digital signature to the check signature; and outputting the digital signature when the digital signature is the same as the check signature.Type: GrantFiled: October 11, 2022Date of Patent: December 24, 2024Assignee: NXP B.V.Inventors: Joost Roland Renes, Melissa Azouaoui, Joppe Willem Bos, Björn Fay, Tobias Schneider
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Patent number: 12170512Abstract: An embodiment of passive phase shifter comprises a ground shield, a pair of ground walls electrically connected to the ground shield having a first height above the ground shield; and a signal line positioned between the ground walls and electrically isolated from the ground shield. The signal line may comprise an intermediate signal line separated a second height above the ground shield; a top signal line separated from the intermediate signal line at a third height above the ground shield and electrically connected to the intermediate signal line by one or more conductive vias; and a plurality of blocks positioned between and electrically isolated from the intermediate signal line and the top signal line.Type: GrantFiled: August 15, 2022Date of Patent: December 17, 2024Assignee: NXP B.V.Inventor: Olivier Tesson
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Patent number: 12164781Abstract: An integrated circuit (IC) includes a memory that stores a thread and a processor that generates an instruction request to retrieve one or more instructions of the thread. The IC further includes an error control circuit that receives the instruction request from the processor and retrieves an instruction of the thread from the memory based on the instruction request. Further, the error control circuit determines whether the retrieved instruction is erroneous. Based on the determination that the retrieved instruction is erroneous, the error control circuit provides a substitute instruction to the processor as a response to the instruction request. The substitute instruction is included in an instruction set of the processor. The processor executes the received substitute instruction and suspends an execution of the thread.Type: GrantFiled: March 1, 2022Date of Patent: December 10, 2024Assignee: NXP B.V.Inventors: Arvind Kaushik, Nikhil Sharma, Rushank Patel
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Patent number: 12164326Abstract: A phase shifted clock generator that includes a delay circuit, a capacitor, and a control circuit is provided. The delay circuit receives a reference clock signal and generates a phase shifted clock signal. A phase difference between the phase shifted clock signal and the reference clock signal is controlled based on a delay of the delay circuit. The control circuit controls, based on the phase shifted clock signal and the reference clock signal, a control voltage generated at the capacitor. The control circuit controls the control voltage by charging and discharging the capacitor with a constant current. The delay of the delay circuit is controlled based on the control voltage such that the phase difference between the phase shifted clock signal and the reference clock signal is within a predefined range.Type: GrantFiled: February 14, 2023Date of Patent: December 10, 2024Assignee: NXP B.V.Inventors: Vishwajit Babasaheb Bugade, Anand Kumar Sinha, Krishna Thakur, Siyaram Sahu
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Patent number: 12164427Abstract: An integrated circuit includes a functional core configured to execute functional logic instructions; a functional memory device coupled to the functional core; a safety core configured to execute safety check logic instructions; a monitored address memory device coupled to the functional core and the safety core, the monitored address memory device configured to store memory addresses to be monitored; and a first safety memory device coupled to the functional memory device and the safety core. When a value in one of the monitored memory addresses changes, the changed value of the one of the monitored memory addresses is stored in the functional memory device and in the first safety memory device. The safety core performs a safety check on the changed value of the one of the monitored memory addresses stored in the first safety memory device.Type: GrantFiled: March 21, 2023Date of Patent: December 10, 2024Assignee: NXP B.V.Inventor: Antoine Fabien Dubois
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Patent number: 12164369Abstract: A system-on-chip (SoC) may include a plurality of terminals and a plurality of terminal controllers. Each terminal controller is configured to selectively disable a terminal. An SoC be configured to execute at least one application. An SoC may include a memory configured to store a plurality of terminal masks. Each terminal mask identifies a subset of the plurality of terminals to be disabled. An SoC may include a fault collection and reaction system configured to transmit, to the plurality of terminal controllers, a fault indication signal in response to an error in a corresponding application. Each terminal controller is further configured to determine, based on a fault indication signal and a value in a terminal mask, whether the terminal corresponding to the terminal controller is to be disabled, and when the terminal corresponding to the terminal controller is to be disabled, disable the terminal.Type: GrantFiled: January 10, 2023Date of Patent: December 10, 2024Assignee: NXP B.V.Inventors: Ankush Sethi, Rohit Kumar Kaul, Aarul Jain
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Patent number: 12164401Abstract: A memory built in self test (MBIST) controller of an MBIST circuit outputs first data. One or more errors is injected in the first data to produce second data. The second data is stored in the memory block. The memory block outputs the second data stored in the memory block. The MBIST controller receives the second data and detects an error in the second data based on a comparison with the first data, the error indicative of a failure of the MBIST. The MBIST controller provides an indication of failure of the MBIST to a processing core external to the MBIST circuit which performs diagnostic action in response to receiving the indication of failure of the MBIST. The processing core validates implementation of the diagnostic action.Type: GrantFiled: May 17, 2023Date of Patent: December 10, 2024Assignee: NXP B.V.Inventors: Umesh Pratap Singh, Ajay Sharma, Ruchi Bora, Ashish Goel
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Patent number: 12166879Abstract: Various embodiments relate to a data processing system including instructions embodied in a non-transitory computer readable medium, the instructions for a cryptographic operation using masked coefficients of a polynomial having d arithmetic shares for lattice-based cryptography in a processor, the instructions, including: shifting an arithmetic share of the d arithmetic shares by a first bound ?0; converting the d shifted arithmetic shares to d Boolean shares; securely subtracting the first bound ?0 and a second bound ?1 from the Boolean shares to obtain z?B,k+1 having d shares, wherein k is the number of bits in the masked coefficients of the polynomial; setting the shares of a boundary check bit to a sign bit of z?B,k+1; and carrying out a cryptographic operation using the d arithmetic shares of the polynomial when the d shares of the boundary check bit indicate that the coefficients of the polynomial are within the first bound ?0 and second bound ?1.Type: GrantFiled: July 11, 2022Date of Patent: December 10, 2024Assignee: NXP B.V.Inventors: Olivier Bronchain, Tobias Schneider
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Patent number: 12159042Abstract: It is described an electronic device, comprising a secure element domain that further comprises: i) a physical memory region configured to store a plurality of data sets; and ii) a control device, coupled to the physical memory region, and configured to transfer at least one data set away from the physical memory region, wherein transferring the data set comprises at least one of: a) transferring the data set as a first data blob to a virtual memory region of the secure element domain; b) off-loading the data set as a second data blob to an external domain.Type: GrantFiled: March 16, 2023Date of Patent: December 3, 2024Assignee: NXP B.V.Inventors: Giten Kulkarni, Andreas Lessiak
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Patent number: 12155127Abstract: A multiple-input multiple-output (MIMO) antenna system for a mobile cellular network and method is described. The MIMO antenna system includes an array of dual-polarization patch antennas each having first and second polarization feed-points, a first polarization radio chain and a second polarization radio chain. The MIMO antenna system includes a beamformer coupled to the first and second polarization radio chains. The beamformer includes a beamformer channel for a respective feedpoint and further includes a transmit amplifier and a detector (coupler) coupled to a transmit amplifier output. In one mode of operation, a signal is transmitted via the first polarization feed-point of a dual-polarisation patch antennas and a replica of the transmitted signal may be sensed using the coupler at the output of the transmit amplifier and routed via the second polarization radio chain to a digital predistortion module.Type: GrantFiled: November 2, 2022Date of Patent: November 26, 2024Assignee: NXP B.V.Inventors: Lucas Maria Florentinus De Maaijer, Mustafa Acar, Paul Mattheijssen